What determines the element count for vwsubu.wv?
Body elements satisfy vstart<=i<vl; with vm=0, v0.mask[i]=1 is also required for activity. SEW/LMUL determine register layout and VLMAX; tail policy does not change the active-element count.
VWSUBU.WV
RISC-V VWSUBU.WV Instruction Details
Instruction ManualV-typeVWSUBU.WV performs unsigned widening subtraction.
Instruction Syntax
vwsubu.wv vd, vs2, vs1, vm
Operand Breakdown
vd has EEW=2*SEW and EMUL=2*LMUL<=8; vs2 is a 2*SEW/2*LMUL wide source, and the second source is SEW/LMUL vs1. Wide groups align to their size.
32-bit OP-V: opcode=1010111, funct6=110110, funct3=010 (OPMVV); vm bit25, vs2 bits24:20, vs1 bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Zero-extend narrow sources to 2*SEW, subtract the second source from vs2 and keep low 2*SEW bits without accumulating old vd. Equal same-width sources require equal initial values. No saturation, vxrm use or vxsat change.
Narrow sources overlap wide vd only with EMUL>=1 and equal highest registers, forcing mask/tail-agnostic behavior. Equal-width vd/vs2 may overlap; narrow vs1 cannot overlap wide vs2. Masked vd excludes v0, which cannot supply mask and data together. Prestart stays unchanged; inactive/tail follow vma/vta, retaining old values or allowing all ones, without guaranteed zeroing.
RV32/RV64 V 1.0; require enabled vector state, vill=0 and support for the selected SEW and 2*SEW; SEW=64 needs additional 128-bit integer elements. Active elements satisfy vstart<=i<vl with masking enabled; vstart>=vl (including vl=0) updates nothing. Implementations may reject nonzero vstart values they cannot produce; success resets vstart=0. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
VVector Operations
Extension condition: RV32/RV64 V 1.0; require enabled vector state, vill=0 and support for the selected SEW and 2*SEW; SEW=64 requires additional 128-bit integer element support.
Instruction Behavior
vwsubu.wv is a V extension unsigned widening subtraction instruction. For active elements, vs2 is read as an unsigned 2*SEW value and the SEW-wide vs1 value is zero-extended to 2*SEW then subtracted from vs2, writing a 2*SEW-wide vd result.
VWSUBU.WV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWSUBU subtracts a zero-extended SEW second source from a 2*SEW-wide vs2 value and writes a 2*SEW-wide vd result.
Instruction input
vwsubu.wv
Teaching context: V 1.0, enabled vector state and valid supported vtype; fix LMUL=m1, VLEN=4096, vstart=0, VLMAX=4096/16. Enter nonnegative bit patterns. Require SEW and 2*SEW support; SEW=64 needs additional 128-bit integer elements beyond baseline V guarantees. Read 32-bit vs2 and a SEW-bit second source; zero-extend narrow sources, subtract the second source from vs2 and keep low 32 bits, without saturation, vxrm use or vxsat change. Wide vs2 has EMUL=2 and an even start; narrow vs1 cannot overlap wide vs2; equal-width vd/vs2 may overlap. Wide vd has EMUL=2 and an even start; a narrow source may overlap only its highest register, forcing mask- and tail-agnostic behavior. Scalars first follow XLEN/SEW conversion: take low bits if wider, sign-extend if narrower, then zero-extend to 2*SEW; x0 supplies zero. With v0.t, vd and data sources exclude v0. Only body is shown; inactive/tail follow vma/vta without definite displayed values. VL=0 updates nothing; success resets vstart=0. Stages are teaching steps, not processor cycles.
Execution Context
OP-V encodingvwsubu.wv
funct6
110110
vm
0
vs2
01000
vs1
01100
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xffffffdf
0x00007fff
0x00010020
0x00001020
0xffffffdf
0x00007fff
0x00010020
0x00001020
w-
w-
w-
w-
w-
w-
w-
w-
v12
0x0011
0x0001
0xffff
0x0013
0x0011
0x0001
0xffff
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwsubu.wv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer unsigned widening subtraction, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VWSUBU.WV subtracts zero-extended SEW vs1 from unsigned 2*SEW vs2; vl, vtype, vstart, and optional v0.t masking determine the active elements.
Official syntax is `vwsubu.wv vd, vs2, vs1, vm`; without a mask operand it is unmasked, while `, v0.t` updates only selected active elements.
32-bit OP-V: opcode=1010111, funct6=110110, funct3=010 (OPMVV); vm is bit25, vs2 bits24:20, vs1 bits19:15, vd bits11:7.
vs2 is read as an unsigned 2*SEW value; the SEW-wide vs1 value is zero-extended to 2*SEW and subtracted from vs2, writing a 2*SEW-wide vd result.
Without a source/destination overlap at different EEWs, tail elements and masked-off elements follow the current vtype tail/mask policy. A legal 2*SEW-destination/SEW-source overlap is mask- and tail-agnostic regardless of vtype; the mnemonic alone does not imply zeroing.
The .w suffix means a wide source participates; this is not ordinary narrow vector subtraction.
Results wrap at 2*SEW; vd has EMUL=2*LMUL<=8 and wide groups align to their size. Active elements satisfy vstart<=i<vl with masking enabled; prestart stays unchanged, and vstart>=vl (including vl=0) updates no destination elements.
Vector Execution Context
vd has EEW=2*SEW and EMUL=2*LMUL<=8; vs2 is a 2*SEW/2*LMUL wide source, and the second source is SEW/LMUL vs1. Wide groups align to their size.
32-bit OP-V: opcode=1010111, funct6=110110, funct3=010 (OPMVV); vm bit25, vs2 bits24:20, vs1 bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Zero-extend narrow sources to 2*SEW, subtract the second source from vs2 and keep low 2*SEW bits without accumulating old vd. Equal same-width sources require equal initial values. No saturation, vxrm use or vxsat change.
Narrow sources overlap wide vd only with EMUL>=1 and equal highest registers, forcing mask/tail-agnostic behavior. Equal-width vd/vs2 may overlap; narrow vs1 cannot overlap wide vs2. Masked vd excludes v0, which cannot supply mask and data together. Prestart stays unchanged; inactive/tail follow vma/vta, retaining old values or allowing all ones, without guaranteed zeroing.
RV32/RV64 V 1.0; require enabled vector state, vill=0 and support for the selected SEW and 2*SEW; SEW=64 needs additional 128-bit integer elements. Active elements satisfy vstart<=i<vl with masking enabled; vstart>=vl (including vl=0) updates nothing. Implementations may reject nonzero vstart values they cannot produce; success resets vstart=0. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
Common Usage Scenarios
Vector Integer Arithmetic
Assume RV32/RV64 V 1.0, enabled vector state, valid supported e16,m1,tu,mu, supported 32-bit results, XLEN=64, VLEN=4096, vl=4, vstart=0, initialized sources, and v0.mask[0..3]=1111. vs2[0]=65536, vs1[0]=1 → vd[0]=65535 (0x0000ffff); other active elements follow the same rule and tails retain old values. Success resets vstart=0.
Unsigned Widening Operations
Assume RV32/RV64 V 1.0, enabled vector state, valid supported e16,m1,tu,mu, supported 32-bit results, XLEN=64, VLEN=4096, vl=4, vstart=0, initialized sources, and v0.mask[0..3]=1111. vs2[0]=65536, vs1[0]=1 → vd[0]=65535 (0x0000ffff); other active elements follow the same rule and tails retain old values. Success resets vstart=0.
Vectorized Loops
Assume RV32/RV64 V 1.0, enabled vector state, valid supported e16,m1,tu,mu, supported 32-bit results, XLEN=64, VLEN=4096, vl=4, vstart=0, initialized sources, and v0.mask[0..3]=1111. vs2[0]=65536, vs1[0]=1 → vd[0]=65535 (0x0000ffff); other active elements follow the same rule and tails retain old values. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- vd has EEW=2*SEW and EMUL=2*LMUL<=8; vs2 is a 2*SEW/2*LMUL wide source, and the second source is SEW/LMUL vs1. Wide groups align to their size.
- 32-bit OP-V: opcode=1010111, funct6=110110, funct3=010 (OPMVV); vm bit25, vs2 bits24:20, vs1 bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Semantic Check
- Zero-extend narrow sources to 2*SEW, subtract the second source from vs2 and keep low 2*SEW bits without accumulating old vd. Equal same-width sources require equal initial values. No saturation, vxrm use or vxsat change.
- Narrow sources overlap wide vd only with EMUL>=1 and equal highest registers, forcing mask/tail-agnostic behavior. Equal-width vd/vs2 may overlap; narrow vs1 cannot overlap wide vs2. Masked vd excludes v0, which cannot supply mask and data together. Prestart stays unchanged; inactive/tail follow vma/vta, retaining old values or allowing all ones, without guaranteed zeroing.
- RV32/RV64 V 1.0; require enabled vector state, vill=0 and support for the selected SEW and 2*SEW; SEW=64 needs additional 128-bit integer elements. Active elements satisfy vstart<=i<vl with masking enabled; vstart>=vl (including vl=0) updates nothing. Implementations may reject nonzero vstart values they cannot produce; success resets vstart=0. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
Pitfalls / Common Confusions
In .w forms, vs2 is the wide source operand; do not read it as two narrow sources.
The result is a 2*SEW integer subtraction; it does not use vxrm and does not set vxsat.
The destination group is wider and must satisfy V extension EMUL and overlap constraints.
FAQ
Does vwsubu.wv always process the whole vector register?
No. V instructions operate on active elements; register grouping and inactive-element behavior are controlled by vtype and policy bits.