Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VWSUBU.WX
RISC-V VWSUBU.WX Instruction Details
Instruction ManualV-typeVWSUBU.WX performs unsigned widening subtraction.
Instruction Syntax
vwsubu.wx vd, vs2, rs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector Operations
Instruction Behavior
vwsubu.wx is a V extension unsigned widening subtraction instruction. For active elements, vs2 is read as an unsigned 2*SEW value and x[rs1] is converted to a SEW value by the .vx rule, zero-extended to 2*SEW, and subtracted from vs2 to write a 2*SEW-wide vd result.
VWSUBU.WX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWSUBU subtracts a zero-extended SEW second source from a 2*SEW-wide vs2 value and writes a 2*SEW-wide vd result.
Instruction input
vwsubu.wx
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. The wide vd destination has EMUL=2 and must start at an even register; if it overlaps a SEW source, that source must be the highest-numbered register in the destination group. Such a legal different-EEW overlap is mask- and tail-agnostic regardless of vtype.vma/vta.In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvwsubu.wx
funct6
110110
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xffffffdf
0x00007fff
0x00010020
0x00001020
0xffffffdf
0x00007fff
0x00010020
0x00001020
w-
w-
w-
w-
w-
w-
w-
w-
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwsubu.wx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer unsigned widening subtraction, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VWSUBU.WX subtracts a SEW scalar, formed by the .vx rule and zero-extended, from unsigned 2*SEW vs2; vl, vtype, vstart, and optional v0.t masking determine the active elements.
Official syntax is `vwsubu.wx vd, vs2, rs1, vm`; without a mask operand it is unmasked, while `, v0.t` updates only selected active elements.
vs2 is read as an unsigned 2*SEW value; XLEN>SEW takes the low SEW bits of x[rs1], while XLEN<SEW sign-extends it to SEW; that SEW bit pattern is zero-extended to 2*SEW and subtracted from vs2, writing a 2*SEW-wide vd result.
Without a source/destination overlap at different EEWs, tail elements and masked-off elements follow the current vtype tail/mask policy. A legal 2*SEW-destination/SEW-source overlap is mask- and tail-agnostic regardless of vtype; the mnemonic alone does not imply zeroing.
The .w suffix means a wide source participates; this is not ordinary narrow vector subtraction.
Vector Execution Context
When reading VWSUBU.WX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Vector Integer Arithmetic
Understand this scenario with real code like «vwsubu.wx v8, v12, x5, v0.t».
Unsigned Widening Operations
Understand this scenario with real code like «vwsubu.wx v8, v12, x5, v0.t».
Vectorized Loops
Understand this scenario with real code like «vwsubu.wx v8, v12, x5, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is V-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
In .w forms, vs2 is the wide source operand; do not read it as two narrow sources.
The result is a 2*SEW integer subtraction; it does not use vxrm and does not set vxsat.
The destination group is wider and must satisfy V extension EMUL and overlap constraints.
FAQ
What determines the element count for vwsubu.wx?
The current vl and vtype determine it, with vstart, LMUL, SEW, mask state, and tail policy also affecting execution.
Does vwsubu.wx always process the whole vector register?
No. V instructions operate on active elements; register grouping and inactive-element behavior are controlled by vtype and policy bits.