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CSR Bit Fields

RISC-V pmpaddr29 CSR Register

Address 0x3CDPrivilege MachineAccess RW / MXLEN: RV32 encodes PA[33:2]; RV64 [53:0] encodes PA[55:2] and [63:54] is zeroMachine physical memory protection CSRs

pmpaddr29 (0x3CD) is the WARL address register for machine PMP entry 29 when 64 PMP entries are implemented; it encodes physical address bits 33:2 on RV32 and 55:2 on RV64.

Related Search Terms
pmpaddr29 CSRpmpaddr29 0x3CDpmpaddr29 TORpmpaddr29 NAPOTpmpaddr29 grainpmp29cfg A
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
063:54WARL/reads zeroaddress[55:2]53:0WARL/may be RO0
Field Map

Understand pmpaddr29 By Bit Fields

2 key fields
63:54

0

WARL/reads zero

RV64: the upper ten bits are zero in the standard pmpaddr format; this segment is part of the WARL format.

0 (bits 63:54) — RV64: the upper ten bits are zero in the standard pmpaddr format; this segment is part of the WARL format.

What This Field Controls

  • - RV64: the upper ten bits are zero in the standard pmpaddr format; this segment is part of the WARL format.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
53:0

address[55:2]

WARL/may be RO0

RV64: encodes bits 55:2 of a 56-bit physical address. Unimplemented physical-address bits make the field WARL; every PMP CSR field may be implemented as read-only zero.

address[55:2] (bits 53:0) — RV64: encodes bits 55:2 of a 56-bit physical address. Unimplemented physical-address bits make the field WARL; every PMP CSR field may be implemented as read-only zero.

What This Field Controls

  • - RV64: encodes bits 55:2 of a 56-bit physical address. Unimplemented physical-address bits make the field WARL; every PMP CSR field may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

pmpaddr29 is the MXLEN-bit WARL address encoding for entry 29 when 64 PMP entries are implemented. pmp29cfg.A determines its meaning; TOR uses pmpaddr28 as the lower bound.

RV32 pmpaddr encodes PA[33:2]; RV64 [53:0] encodes PA[55:2], with [63:54] zero.
TOR entry 29 uses pmpaddr28 as its lower bound and pmpaddr29 as its upper bound; NAPOT uses low pmpaddr29 bits to encode a naturally aligned power-of-two region of at least 8 bytes.
Platform grain changes low-bit readback; pmp29cfg.L or a locked TOR entry 30 can cause writes to pmpaddr29 to be ignored. Smepmp MML=1 changes L's permission meaning, but the relevant L=1 rules remain locked unless RLB=1 temporarily bypasses locking.
RISC-V ISA Manual 2026-07-09 release - Machine ISA PMPRISC-V Privileged Architecture - Physical Memory ProtectionRISC-V Privileged Architecture - Smepmp Physical Memory Protection Rules

What To Check First When Reading This CSR

  • - PMP is optional; implementations may provide 0, 16, or 64 entries, with the lowest-numbered entries implemented first. Therefore, pmpaddr29 exists only when 64 entries are implemented; every PMP CSR field is WARL and may be read-only zero.
  • - pmpaddr29 is accessible only to M-mode. Its readback depends on pmp29cfg.A and the platform-wide PMP grain G.
  • - With G>=2 and A=NAPOT, pmpaddr29[G-2:0] reads as ones; with G>=1 and A=OFF/TOR, pmpaddr29[G-1:0] reads as zeros, but those bits do not affect TOR matching. Changing pmp29cfg.A[1] changes readback, not the underlying stored value.
  • - Reset specifies defaults only for writable PMP A/L fields (subject to platform overrides); pmpaddr29's reset value is unspecified, but no WARL field contains an illegal value.

Risk Checks Before Writing

  • - Writes to pmpaddr29 are ignored when pmp29cfg.L=1; pmpaddr29 is also unwritable as entry 30's lower bound when that entry is locked with pmp30cfg.A=TOR. Without Smepmp, locking persists until hart reset. With Smepmp MML=1, L changes permission meaning, but the L=1 M-mode-only or locked Shared-Region rules it defines remain locked unless mseccfg.RLB=1 temporarily bypasses locking.
  • - pmpaddr29 is WARL; read it back after writing and interpret the masked value using the current pmp29cfg.A and grain.
  • - With pmp29cfg.A=TOR, entry 29 matches pmpaddr28 <= y < pmpaddr29; if the lower bound is not less than the upper bound, it matches no addresses. NA4 is not selectable when G>=1.

Put It Back Into A Real Flow

1

Read pmp29cfg.A to determine whether entry 29 uses OFF, TOR, NA4, or NAPOT.

2

Write pmpaddr29 for the selected mode; TOR also requires lower bound pmpaddr28, while NAPOT encodes range size in low bits.

3

Read back pmpaddr29 and the corresponding pmpcfg CSR to confirm the effective WARL/grain encoding; set pmp29cfg.L only after final verification.

FAQ

Where do pmpaddr29's TOR bounds come from?

With pmp29cfg.A=TOR, pmpaddr28 supplies the lower bound and pmpaddr29 the upper bound, so entry 29 matches the half-open range pmpaddr28 <= y < pmpaddr29; it matches no addresses when the lower bound is not less than the upper bound.

Why can pmpaddr29 read back differently from the written value?

pmpaddr29 is WARL, and platform grain plus pmp29cfg.A[1] masks low-bit readback: NAPOT can read ones while OFF/TOR reads zeros. Changing A[1] does not alter the underlying stored value.