How do RV32 and RV64 results differ?
RV64 C/Zca writes one 64-bit register. RV32 requires Zclsd and writes an even/odd pair; the lower register receives the low 32 bits regardless of endianness.
C.LD
RISC-V C.LD Instruction Details
Instruction ManualC-typeRV64 C/Zca: load a 64-bit doubleword from rs1' plus offset; RV32 Zclsd: load into an even/odd register pair.
Instruction Syntax
c.ld rd', offset(rs1')
Operand Breakdown
RV64 C/Zca or RV32 Zclsd; 16-bit CL format. Zclsd requires Zilsd and Zca, and conflicts with Zcf.
Three-bit rd' and rs1' select x8–x15; byte offset 0–248, step eight.
Add the zero-extended offset to the base before writeback. RV64 writes one 64-bit register; RV32 writes low/high 32 bits to even rd and rd+1.
An 8-byte address is naturally aligned; an RV32 pair access is not necessarily atomic as a whole. On a trap the base retains its original value, but other destinations may have been updated.
CZcaZclsdCompressed Instruction
Instruction Behavior
C.LD uses CL format with base rs1'. The byte offset is 0–248 in multiples of eight, already including scaling; add its zero-extended value to the old base. On RV64 C/Zca, a completed access writes 64 bits to rd'. On RV32 Zclsd, the even destination and following odd register receive the low/high 32 bits. Three-bit rd' and rs1' both select x8–x15.
C.LD Decode & Execute Animation
Shows only official 16-bit fields, address/immediate calculation, and architectural state; it does not simulate a pipeline, cache, endianness implementation, or timing.
c.ld, ()
Execution context
RV64 C / Zca
An address divisible by 8 is naturally aligned, so the address-misaligned option does not apply; access faults remain possible. The EEI defines misaligned completion. Memory values are already interpreted using EEI endianness.
x[rs1'] + 16 -> 0x0000000000002010; mem[0x0000000000002010][63:0] = 0x0123456789ABCDEF
16-bit encoding fields
15..13
funct3
011
12..10
uimm[5:3]
010
9..7
rs1'
010
6..5
uimm[7:6]
00
4..2
rd'
000
1..0
op
00
Execution data path
Compressed fields: rd'=000 -> x8, rs1'=010 -> x10, uimm=16. inst[12:10|6:5] -> uimm[5:3|7:6]; low[2:0]=000 -> 16 bytes (EXTZ)
(0x0000000000002000 + 16) mod 2^64 = 0x0000000000002010
mem[0x0000000000002010][63:0] = 0x0123456789ABCDEF
Architectural state has not been committed.
Quick Understanding & Search Notes
RV64 C/Zca: load a 64-bit doubleword from rs1' plus offset; RV32 Zclsd: load into an even/odd register pair.
16-bit CL encoding; rd' and rs1' select x8–x15.
Reconstruct the 0–248 byte offset with three implicit zero low bits.
Natural alignment only excludes address-misaligned exceptions; permissions or memory regions can still cause access faults.
Common Usage Scenarios
Doubleword data load
RV64 C/Zca, x10=0x2000 and mem64[0x2010] = 0x0123456789abcdef, with a completed access: c.ld x8, 16(x10) writes that 64-bit value to x8. On RV32 Zclsd, the same completed access writes x8=0x89abcdef and x9=0x01234567.
Pre-Use Checklist
Syntax Check
- RV64 C/Zca or RV32 Zclsd; 16-bit CL format. Zclsd requires Zilsd and Zca, and conflicts with Zcf.
- Three-bit rd' and rs1' select x8–x15; byte offset 0–248, step eight.
Semantic Check
- Add the zero-extended offset to the base before writeback. RV64 writes one 64-bit register; RV32 writes low/high 32 bits to even rd and rd+1.
- An 8-byte address is naturally aligned; an RV32 pair access is not necessarily atomic as a whole. On a trap the base retains its original value, but other destinations may have been updated.
Pitfalls / Common Confusions
The byte offset is 0–248, step eight; do not multiply it by eight again.
RV32 Zclsd requires Zilsd and Zca, conflicts with Zcf, and requires an even destination.
An 8-byte address is naturally aligned but does not guarantee an atomic 64-bit pair access; 4-byte alignment guarantees atomic word accesses but may still trap for misalignment.
On an RV32 pair-load trap, the base must retain its original value; other destination registers may have been partially updated. Do not assume complete rollback.
FAQ
Are destinations always unchanged on a load trap?
RV32 Zclsd makes no such guarantee: the base retains its original value, but other destinations may have been updated. Only a completed load delivers the full pair result.