RISC-V C.LD Instruction Details

Instruction ManualC-type

RV64C: compressed 64-bit doubleword load; RV32 Zclsd: compressed load of a 64-bit value into an even/odd register pair.

Instruction Syntax

c.ld rd', offset(rs1')

Operand Breakdown

Compressed instructions are 16 bits; registers are often limited to x8–x15.

Immediate fields are narrower. Refer to the full encoding for this compressed instruction.

CZclsdCompressed Instruction

Related Search Terms

C.LD instruction RISC-V C.LD c.ld syntax c.ld encoding c.ld C/Zclsd c.ld compressed instruction compressed doubleword load

Instruction Behavior

C.LD (CL format, rd' and rs1' x8-x15, RV64C only) loads 64-bit value from address rs1' + zero-extended offset (×8) into rd'. Expands to ld rd',offset(rs1'). Part of Zclsd (or C extension for RV64C).

Quick Understanding & Search Notes

C.LD is the 16-bit encoding form for compressed doubleword load; its semantics and encodable register/immediate ranges must be read from the official C extension rules.

Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.

Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.

RISC-V Unprivileged ISA Manual, C Extension

Common Usage Scenarios

Compressed & Code Size

Understand this scenario with real code like «c.ld x8, 0(x10)».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is C-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

In RV64C this is a normal 64-bit register load; in RV32 Zclsd it loads a register pair.

Zclsd depends on Zilsd and Zca and applies only to RV32.

The Zclsd destination must denote a valid even/odd register pair; reserved encodings must not be used.

FAQ

Is it always equivalent to a same-named 32-bit instruction?

Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.

Why do register restrictions matter?

Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.