Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.LDSP
RISC-V C.LDSP Instruction Details
Instruction ManualC-typeRV64C: compressed 64-bit doubleword load; RV32 Zclsd: compressed load of a 64-bit value into an even/odd register pair.
Instruction Syntax
c.ldsp rd, offset(sp)
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CZclsdCompressed Instruction
Instruction Behavior
C.LDSP uses the CI format and loads a 64-bit value from sp (x2) plus a zero-extended, 8-byte-scaled offset. In RV64C it writes any non-x0 rd; in RV32 Zclsd it writes an even/odd register pair and rd must be nonzero and even.
C.LDSP Decode & Execute Animation
Shows only official 16-bit fields, address/immediate calculation, and architectural state; it does not simulate a pipeline, cache, endianness implementation, or timing.
c.ldsp, (sp)
Execution context
The EEI choice affects this result only when the effective address is not divisible by 8; a naturally aligned access must not raise an address-misaligned exception.
x[sp/x2] + 16 -> 0x0000000000002010; mem[0x0000000000002010][63:0] = 0x0123456789ABCDEF
16-bit encoding fields
15..13
funct3
011
12
uimm[5]
0
11..7
rd
00001
6..5
uimm[4:3]
10
4..2
uimm[8:6]
000
1..0
op
10
Execution data path
x2/sp is fixed as the base; rd field 00001 -> x1; scattered uimm reconstructs 16.
0x0000000000002000 + 16 = 0x0000000000002010
mem[0x0000000000002010][63:0] = 0x0123456789ABCDEF
Architectural state has not been committed.
Quick Understanding & Search Notes
C.LDSP is the 16-bit encoding form for compressed stack doubleword load; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Register Operations
Understand this scenario with real code like «c.ldsp x10, 16(sp) # x10 = *(sp+16)».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
In RV64C this is a normal 64-bit register load; in RV32 Zclsd it loads a register pair.
Zclsd depends on Zilsd and Zca and applies only to RV32.
The Zclsd destination must denote a valid even/odd register pair; reserved encodings must not be used.
An RV32 Zclsd doubleword access is naturally aligned only at an 8-byte address; at a 4-byte but not 8-byte address each word access is required to be atomic, but a misaligned trap remains possible.
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.