How do RV32 and RV64 results differ?
RV64 C/Zca writes one 64-bit register. RV32 requires Zclsd and writes an even/odd pair; the lower register receives the low 32 bits regardless of endianness.
C.LDSP
RISC-V C.LDSP Instruction Details
Instruction ManualC-typeRV64 C/Zca: load a 64-bit doubleword from sp/x2 plus offset; RV32 Zclsd: load into an even/odd register pair.
Instruction Syntax
c.ldsp rd, offset(sp)
Operand Breakdown
RV64 C/Zca or RV32 Zclsd; 16-bit CI format. Zclsd requires Zilsd and Zca, and conflicts with Zcf.
Full five-bit rd selects x1–x31, with x0 reserved; the base is fixed x2/sp. Byte offset 0–504, step eight.
Add the zero-extended offset to the base before writeback. RV64 writes one 64-bit register; RV32 writes low/high 32 bits to even rd and rd+1.
An 8-byte address is naturally aligned; an RV32 pair access is not necessarily atomic as a whole. On a trap the base retains its original value, but other destinations may have been updated.
CZcaZclsdCompressed Instruction
Instruction Behavior
C.LDSP uses CI format with base sp/x2. The byte offset is 0–504 in multiples of eight, already including scaling; add its zero-extended value to the old base. On RV64 C/Zca, a completed access writes 64 bits to rd. On RV32 Zclsd, the even destination and following odd register receive the low/high 32 bits. rd is a full five-bit field; x0 is reserved.
C.LDSP Decode & Execute Animation
Shows only official 16-bit fields, address/immediate calculation, and architectural state; it does not simulate a pipeline, cache, endianness implementation, or timing.
c.ldsp, (sp)
Execution context
RV64 C / Zca
An address divisible by 8 is naturally aligned, so the address-misaligned option does not apply; access faults remain possible. The EEI defines misaligned completion. Memory values are already interpreted using EEI endianness.
x[sp/x2] + 16 -> 0x0000000000002010; mem[0x0000000000002010][63:0] = 0x0123456789ABCDEF
16-bit encoding fields
15..13
funct3
011
12
uimm[5]
0
11..7
rd
00001
6..5
uimm[4:3]
10
4..2
uimm[8:6]
000
1..0
op
10
Execution data path
x2/sp is fixed as the base; rd field 00001 -> x1; scattered uimm reconstructs 16. inst[12|6:5|4:2] -> uimm[5|4:3|8:6]; low[2:0]=000 -> 16 bytes (EXTZ)
(0x0000000000002000 + 16) mod 2^64 = 0x0000000000002010
mem[0x0000000000002010][63:0] = 0x0123456789ABCDEF
Architectural state has not been committed.
Quick Understanding & Search Notes
RV64 C/Zca: load a 64-bit doubleword from sp/x2 plus offset; RV32 Zclsd: load into an even/odd register pair.
16-bit CI encoding; rd selects x1–x31 with fixed base sp/x2.
Reconstruct the 0–504 byte offset with three implicit zero low bits.
Natural alignment only excludes address-misaligned exceptions; permissions or memory regions can still cause access faults.
Common Usage Scenarios
Stack-relative doubleword load
RV64 C/Zca, old sp=0x2000 and mem64[0x2010] = 0x0123456789abcdef, with a completed access: c.ldsp x10, 16(sp) writes x10. RV32 Zclsd writes x10=0x89abcdef and x11=0x01234567, leaving sp unchanged.
Pre-Use Checklist
Syntax Check
- RV64 C/Zca or RV32 Zclsd; 16-bit CI format. Zclsd requires Zilsd and Zca, and conflicts with Zcf.
- Full five-bit rd selects x1–x31, with x0 reserved; the base is fixed x2/sp. Byte offset 0–504, step eight.
Semantic Check
- Add the zero-extended offset to the base before writeback. RV64 writes one 64-bit register; RV32 writes low/high 32 bits to even rd and rd+1.
- An 8-byte address is naturally aligned; an RV32 pair access is not necessarily atomic as a whole. On a trap the base retains its original value, but other destinations may have been updated.
Pitfalls / Common Confusions
The byte offset is 0–504, step eight; do not multiply it by eight again.
RV32 Zclsd requires Zilsd and Zca, conflicts with Zcf, and requires an even destination.
An 8-byte address is naturally aligned but does not guarantee an atomic 64-bit pair access; 4-byte alignment guarantees atomic word accesses but may still trap for misalignment.
On an RV32 pair-load trap, the base must retain its original value; other destination registers may have been partially updated. Do not assume complete rollback.
FAQ
Are destinations always unchanged on a load trap?
RV32 Zclsd makes no such guarantee: the base retains its original value, but other destinations may have been updated. Only a completed load delivers the full pair result.