How does the RV32 Zclsd source differ from RV64C?
RV64C reads 64 bits from rs2. RV32 Zclsd requires even rs2 and forms the 64-bit value from rs2's low 32 bits and rs2+1's high 32 bits.
C.SDSP
RISC-V C.SDSP Instruction Details
Instruction ManualC-typeRV64C stores a 64-bit doubleword from rs2; RV32 Zclsd stores a 64-bit value from the even rs2/rs2+1 register pair.
Instruction Syntax
c.sdsp rs2, offset(sp)
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CZclsdCompressed Instruction
Instruction Behavior
C.SDSP uses the CSS format. RV64C stores rs2's 64-bit value at x2/sp plus a zero-extended offset scaled by 8; RV32 Zclsd forms the 64-bit source from even rs2 and rs2+1. Both forms use x2 plus the offset as the effective address.
C.SDSP Decode & Execute Animation
Shows only official 16-bit fields, operands, conditions, and architectural state; it does not model a pipeline, cache, or timing.
c.sdsp,(sp)
Execution context
A naturally aligned access cannot raise an address-misaligned exception; any address can still raise an access-fault according to the EEI's access rules.
mem[0x0000000000002010] <- 0x0123456789ABCDEF
16-bit encoding fields
15..13
funct3
111
12..10
uimm[5:3]
010
9..7
uimm[8:6]
000
6..2
rs2
01010
1..0
op
10
Execution data path
CSS fields: rs2=x10; sp is fixed to x2; uimm=16.
0x0000000000002000 + 16 = 0x0000000000002010; X(x10)[63:0] = 0x0123456789ABCDEF
mem[0x0000000000002010][63:0] <- 0x0123456789ABCDEF
Architectural state has not been committed.
Quick Understanding & Search Notes
C.SDSP fixes the base to x2/sp; CSS offset bits are reconstructed and scaled by 8. RV64C and RV32 Zclsd use different source-register models.
RV64C uses a full five-bit rs2 field; RV32 Zclsd requires even rs2 to encode the rs2/rs2+1 register pair.
The effective address is x2 plus a zero-extended offset scaled by 8; an 8-byte naturally aligned RV32 Zclsd address cannot raise an address-misaligned exception.
Common Usage Scenarios
Stack-frame register saves
Understand this scenario with real code like «c.sdsp x10, 16(sp) # *(sp+16) = x10».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
RV64C reads 64 bits from one rs2; RV32 Zclsd reads low/high 32-bit halves from even rs2 and rs2+1.
Zclsd is RV32-only, depends on Zilsd and Zca, and overlaps Zcf encodings so is incompatible with Zcf.
An odd RV32 Zclsd rs2 encoding is reserved; with rs2=x0 the 64-bit source is zero and x1 is not read.
FAQ
How is an RV32 Zclsd misaligned access handled?
At an 8-byte address it cannot raise an address-misaligned exception. At a 4-byte but not 8-byte address each word access must be atomic, but a misaligned trap remains possible; other misaligned addresses can also trap.