How does the RV32 Zclsd source differ from RV64C?
RV64C reads 64 bits from rs2. RV32 Zclsd requires even rs2: rs2 holds the low 32 bits and rs2+1 the high 32 bits; rs2=x0 makes the whole source zero without reading x1.
C.SDSP
RISC-V C.SDSP Instruction Details
Instruction ManualC-typeRV64C stores a 64-bit doubleword from rs2; RV32 Zclsd stores a 64-bit value from the even rs2/rs2+1 register pair.
Instruction Syntax
c.sdsp rs2, offset(sp)
Operand Breakdown
RV64 C/Zca or RV32 Zclsd; 16-bit CSS format with fixed x2/sp base. Zclsd requires Zilsd and Zca and conflicts with Zcf.
rs2 is a full five-bit field; RV32 requires an even pair, with an entirely zero source and no x1 read for rs2=x0.
uimm[8:0]={inst[9:7],inst[12:10],000}; byte offsets 0–504, step eight, are zero-extended and added to x2 without rescaling.
Completion stores 64 bits. Eight-byte alignment prevents alignment faults; faults may follow partial writes, and RV32 does not guarantee whole-access atomicity even when aligned.
CZclsdCompressed Instruction
Extension condition: RV64 C/Zca; or RV32 Zclsd (requires Zilsd and Zca; incompatible with Zcf).
Instruction Behavior
C.SDSP uses the CSS format. RV64C stores rs2's 64-bit value at x2/sp plus a zero-extended offset scaled by 8; RV32 Zclsd forms the 64-bit source from even rs2 and rs2+1. Both forms use x2 plus the offset as the effective address.
C.SDSP Decode & Execute Animation
Shows only official 16-bit fields, operands, conditions, and architectural state; it does not model a pipeline, cache, or timing.
c.sdsp,(sp)
Execution context
RV64 C/Zca
A naturally aligned access cannot raise an address-misaligned exception; any address can still raise an access-fault according to the EEI's access rules.
0x0000000000002000 + 16 → mem[0x0000000000002010] <- 0x0123456789ABCDEF
16-bit encoding fields
15..13
funct3
111
12..10
uimm[5:3]
010
9..7
uimm[8:6]
000
6..2
rs2
01010
1..0
op
10
Execution data path
CSS fields: rs2=x10; sp is fixed to x2; uimm=16 bytes.
uimm[8:0]={inst[9:7],inst[12:10],000}=000010000=16; EXTZ(uimm)
0x0000000000002000 + 16 = 0x0000000000002010; X(x10)[63:0] = 0x0123456789ABCDEF
mem[0x0000000000002010][63:0] <- 0x0123456789ABCDEF
Architectural state has not been committed.
Quick Understanding & Search Notes
C.SDSP fixes the base to x2/sp; CSS offset bits are reconstructed and scaled by 8. RV64C and RV32 Zclsd use different source-register models.
CSS: inst[12:10]=uimm[5:3], inst[9:7]=uimm[8:6], with three low zeros. The byte offset is 0–504, step eight; do not multiply it again before adding x2.
RV64 uses the full five-bit rs2 to select x0–x31. RV32 Zclsd requires even rs2; low/high halves come from rs2/rs2+1, except rs2=x0 makes the entire 64-bit source zero.
Eight-byte alignment prevents address-misaligned exceptions, but access faults remain possible. RV32 pair accesses need not be atomic even when aligned, and faults may follow partial writes.
Common Usage Scenarios
Stack-frame register saves
RV64 C/Zca, sp=0x2000 and x10=0x0123456789abcdef: c.sdsp x10, 16(sp) stores that mem64 value at 0x2010 on completion. RV32 Zclsd uses x10=0x89abcdef and x11=0x01234567.
Pre-Use Checklist
Syntax Check
- RV64 C/Zca or RV32 Zclsd; 16-bit CSS format with fixed x2/sp base. Zclsd requires Zilsd and Zca and conflicts with Zcf.
- rs2 is a full five-bit field; RV32 requires an even pair, with an entirely zero source and no x1 read for rs2=x0.
Semantic Check
- uimm[8:0]={inst[9:7],inst[12:10],000}; byte offsets 0–504, step eight, are zero-extended and added to x2 without rescaling.
- Completion stores 64 bits. Eight-byte alignment prevents alignment faults; faults may follow partial writes, and RV32 does not guarantee whole-access atomicity even when aligned.
Pitfalls / Common Confusions
RV64C reads 64 bits from one rs2; RV32 Zclsd reads low/high 32-bit halves from even rs2 and rs2+1.
Zclsd is RV32-only, depends on Zilsd and Zca, and overlaps Zcf encodings so is incompatible with Zcf.
An odd RV32 Zclsd rs2 encoding is reserved; with rs2=x0 the 64-bit source is zero and x1 is not read.
FAQ
How is an RV32 Zclsd misaligned access handled?
At an 8-byte address it cannot raise an address-misaligned exception. At a 4-byte but not 8-byte address each word access must be atomic, but a misaligned trap remains possible; other misaligned addresses can also trap.