Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.SDSP
RISC-V C.SDSP Instruction Details
Instruction ManualC-typeRV64C: compressed 64-bit doubleword store; RV32 Zclsd: compressed store of a 64-bit value from an even/odd register pair.
Instruction Syntax
c.sdsp rs2, offset(sp)
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CZclsdCompressed Instruction
Instruction Behavior
C.SDSP (CSS format, rs2 any of 32, RV64C only) stores 64-bit value of rs2 to address sp(x2) + zero-extended offset (×8). Expands to sd rs2,offset(x2).
Quick Understanding & Search Notes
C.SDSP is the 16-bit encoding form for compressed stack doubleword store; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Register Operations
Understand this scenario with real code like «c.sdsp x10, 16(sp) # *(sp+16) = x10».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
In RV64C this is a normal 64-bit register store; in RV32 Zclsd it stores a register pair.
Zclsd depends on Zilsd and Zca and applies only to RV32.
The Zclsd source must denote a valid even/odd register pair; reserved encodings must not be used.
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.