Can C.SD be used on RV32?
With Zclsd: the source is an even/odd pair starting at x8/x10/x12/x14; odd-source encodings are reserved.
C.SD
RISC-V C.SD Instruction Details
Instruction ManualC-typeRV64C stores a 64-bit doubleword from rs2; RV32 Zclsd stores a 64-bit value from the even rs2/rs2+1 register pair.
Instruction Syntax
c.sd rs2', offset(rs1')
Operand Breakdown
RV64 C/Zca or RV32 Zclsd; 16-bit CS format. Zclsd requires Zilsd and Zca, and conflicts with Zcf.
Three-bit rs1'/rs2' fields select x8–x15; RV32 requires an even source. Byte offset 0–248, step eight.
uimm[7:0]={inst[6:5],inst[12:10],000}; zero-extend and add to the base without rescaling the byte offset.
Completion stores 64 bits; RV32 takes low/high halves from rs2'/rs2'+1. Eight-byte alignment prevents alignment faults; faults may follow partial writes.
CZclsdCompressed Instruction
Instruction Behavior
C.SD uses CS format, with base/source fields in x8–x15 and byte offset 0–248 in steps of 8. RV64 C/Zca stores one 64-bit register; RV32 Zclsd stores low 32 bits from even rs2' and high 32 bits from rs2'+1. Zclsd requires Zilsd and Zca, and conflicts with Zcf.
C.SD Decode & Execute Animation
Shows only ISA-visible 16-bit encoding, operands, and state, not a pipeline, cache, or timing.
c.sd,()
Execution context
This animation models the RV64C form; the static detail retains the RV32 Zclsd register-pair condition. The offset is already in bytes. Eight-byte alignment prevents address-misaligned exceptions; the EEI defines misaligned outcomes. mem64 denotes the value without choosing byte order.
0x0000000000002000 + 24 (mod 2^64) -> 0x0000000000002018; mem64 <- 0x0123456789ABCDEF
16-bit encoding fields
15..13
funct3
111
12..10
uimm[5:3]
011
9..7
rs1'
010
6..5
uimm[7:6]
00
4..2
rs2'
001
1..0
op
00
Execution data path
Compressed operand mapping
rs1'=010 -> x(8+2)=x10, rs2'=001 -> x(8+1)=x9; uimm[7:0]={inst[6:5],inst[12:10],000}=00011000 (3 * 8) -> zero-extended byte offset 24
Concrete calculation
The Calculate stage shows the equation for the current inputs.
Architectural result
Continue to Commit result to reveal architectural state.
Quick Understanding & Search Notes
RV64 C/Zca C.SD uses two x8–x15 fields and a zero-extended byte offset (0–248, step 8); RV32 Zclsd uses an even/odd register pair.
rs1' and rs2' map to x8–x15; uimm[7:0]={inst[6:5],inst[12:10],000}, and the assembly offset is already in bytes.
RV32 Zclsd is available only with Zilsd and Zca and without Zcf; rs2' must denote an even/odd register pair, and odd encodings are reserved.
Common Usage Scenarios
Compressed & Code Size
RV64 C/Zca, x10=0x2000 and x8=0x0123456789abcdef: c.sd x8, 0(x10) stores that mem64 value on completion. RV32 Zclsd uses x8=0x89abcdef and x9=0x01234567.
Pre-Use Checklist
Syntax Check
- RV64 C/Zca or RV32 Zclsd; 16-bit CS format. Zclsd requires Zilsd and Zca, and conflicts with Zcf.
- Three-bit rs1'/rs2' fields select x8–x15; RV32 requires an even source. Byte offset 0–248, step eight.
Semantic Check
- uimm[7:0]={inst[6:5],inst[12:10],000}; zero-extend and add to the base without rescaling the byte offset.
- Completion stores 64 bits; RV32 takes low/high halves from rs2'/rs2'+1. Eight-byte alignment prevents alignment faults; faults may follow partial writes.
Pitfalls / Common Confusions
In RV64C this is a normal 64-bit register store; in RV32 Zclsd it stores a register pair.
Zclsd depends on Zilsd and Zca and applies only to RV32.
The Zclsd source must denote a valid even/odd register pair; odd source-register encodings are reserved.
FAQ
Does the aligned offset guarantee access success?
No: the base may be misaligned; EEI rules apply. Faults need not undo partial writes, and RV32 pair stores need not be atomic as a whole.