Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.SD
RISC-V C.SD Instruction Details
Instruction ManualC-typeRV64C stores a 64-bit doubleword from rs2; RV32 Zclsd stores a 64-bit value from the even rs2/rs2+1 register pair.
Instruction Syntax
c.sd rs2', offset(rs1')
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CZclsdCompressed Instruction
Instruction Behavior
C.SD has two extension-defined forms: RV64C CS format stores the 64-bit value of rs2' (x8-x15) to rs1' plus a zero-extended offset scaled by 8, expanding to sd rs2',offset(rs1'); RV32 Zclsd instead stores a 64-bit value from the even/odd rs2', rs2'+1 register pair. Zclsd depends on Zilsd and Zca and is incompatible with Zcf.
C.SD Decode & Execute Animation
Shows only ISA-visible 16-bit encoding, operands, and state, not a pipeline, cache, or timing.
c.sd,()
Execution context
This animation models the RV64C form; the static detail retains the RV32 Zclsd register-pair condition. An 8-byte naturally aligned address must not raise an address-misaligned exception; the EEI decides completion or exception for a misaligned access.
x10 + 24 -> mem[0x0000000000002018] <- 0x0123456789ABCDEF
16-bit encoding fields
15..13
funct3
111
12..10
uimm[5:3]
011
9..7
rs1'
010
6..5
uimm[7:6]
00
4..2
rs2'
001
1..0
op
00
Execution data path
Input to result
x10 + 24 -> mem[0x0000000000002018] <- 0x0123456789ABCDEF
Concrete calculation
The Calculate stage shows the equation for the current inputs.
Architectural state
Architectural state is written only at Commit result.
Architectural result
Continue to Commit result to reveal architectural state.
Quick Understanding & Search Notes
RV64C C.SD uses two x8-x15 compressed-register fields and a zero-extended offset scaled by 8; RV32 Zclsd uses an even/odd register pair.
In the RV64C form, rs1' and rs2' each map to x8-x15; the offset is reconstructed from uimm[5:3|7:6] and scaled by 8.
RV32 Zclsd is available only with Zilsd and Zca and without Zcf; rs2' must denote an even/odd register pair, and odd encodings are reserved.
Common Usage Scenarios
Compressed & Code Size
Understand this scenario with real code like «c.sd x8, 0(x10)».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
In RV64C this is a normal 64-bit register store; in RV32 Zclsd it stores a register pair.
Zclsd depends on Zilsd and Zca and applies only to RV32.
The Zclsd source must denote a valid even/odd register pair; odd source-register encodings are reserved.
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.