Does C.LW zero-extend on RV64?
No; like LW, it sign-extends the loaded 32-bit word to XLEN.
C.LW
RISC-V C.LW Instruction Details
Instruction ManualC-typeLoad a 32-bit word, sign-extend it to XLEN, and write rd'. CL format.
Instruction Syntax
c.lw rd', offset(rs1')
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.LW (CL format, with rd' and rs1' limited to x8-x15) loads a 32-bit word from rs1' plus a zero-extended, 4-byte-scaled offset, sign-extends it to XLEN, and writes rd'. It expands to lw rd', offset(rs1'); the offset range is 0 through 124 bytes.
C.LW Decode & Execute Animation
This interactive model shows only architectural decode, operands, and state changes, not a pipeline, cache, or timing model.
c.lw,()
Execution context
Encoding fields
15..13
funct3
010
12..10
uimm[5:3]
010
9..7
rs1'
010
6
uimm[2]
0
5
uimm[6]
0
4..2
rd'
000
1..0
op
00
Execution data path
Decode
CL: rd' / rs1' / uimm
Operands
x10 = 0x0000000000002000
Execute
EA = 0x0000000000002010
State
x8 <- sext.w
The address is naturally aligned; this example assumes the EEI permits access.
Architectural result
Awaiting state update: the highlighted fields and calculation above show the current step; no architectural result has been committed yet.
Quick Understanding & Search Notes
C.LW uses CL format: rs1' plus a zero-extended, 4-byte-scaled offset forms the address, and the loaded word is sign-extended to XLEN.
Both rd' and rs1' can encode only x8-x15.
The EEI determines completion or an exception for a misaligned effective address.
Common Usage Scenarios
Compressed & Code Size
Understand this scenario with real code like «c.lw x8, 0(x10)».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
rd' and rs1' limited to x8-x15
The offset is zero-extended (not sign-extended), ranges from 0 through 124 bytes, and is scaled by 4; RV64 still sign-extends the loaded 32-bit word
For a misaligned effective address, the EEI determines whether access completes or raises address-misaligned/access-fault