C.LW
RISC-V C.LW Instruction Details
Instruction ManualC-typeLoad 32-bit word from memory into rd'. CL format.
Instruction Syntax
c.lw rd', offset(rs1')
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.LW (CL format, rd' and rs1' x8-x15 only) loads 32-bit value from address rs1' + zero-extended offset (×4) into rd'. Expands to lw rd',offset(rs1'). Offset is zero-extended, scaled by 4.
Common Usage Scenarios
Compressed & Code Size
Understand this scenario with real code like «c.lw x8, 0(x10)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
rd' and rs1' limited to x8-x15
Offset is zero-extended (not sign-extended), range 0-124 bytes (word-aligned)