Does C.LW zero-extend on RV64?
No; like LW, it sign-extends the loaded 32-bit word to XLEN.
C.LW
RISC-V C.LW Instruction Details
Instruction ManualC-typeLoad a 32-bit word, sign-extend it to XLEN, and write rd'. CL format.
Instruction Syntax
c.lw rd', offset(rs1')
Operand Breakdown
C.LW uses the 16-bit CL format; its 3-bit rd' and rs1' fields each select x8-x15.
offset is a zero-extended byte displacement from 0 through 124 in multiples of 4; the byte offset already includes the ×4 scaling.
Base plus offset forms the effective address; a completed 32-bit load is sign-extended to XLEN and written to rd'. The EEI defines misaligned outcomes.
CCompressed Instruction
Extension condition: RV32C / RV64C; this page describes C extension version 2.0.
Instruction Behavior
C.LW (CL format, with rd' and rs1' limited to x8-x15) loads a 32-bit word from rs1' plus a zero-extended, 4-byte-scaled offset, sign-extends it to XLEN, and writes rd'. It expands to lw rd', offset(rs1'); the offset range is 0 through 124 bytes.
C.LW Instruction Animation
Three learning stages illustrate architectural rules, without modeling processor pipelines or cycles.
c.lw,()
Execution context
RV32C / RV64C; C sets IALIGN=16, so PC is an even byte address. Address arithmetic wraps at XLEN. The example assumes an EEI-permitted memory access; the chosen EEI outcome applies only to misalignment. Natural alignment does not exclude other access exceptions.
c.lw → x8 ← 0xFFFFFFFFFFFFFF80; PC ← 0x0000000000001002
16-bit encoding fields
0x4900
15..13
funct3
010
12..10
uimm[5:3]
010
9..7
rs1'
010
6
uimm[2]
0
5
uimm[6]
0
4..2
rd'
000
1..0
op
00
Operands and calculation
Restore compressed operands
rs1'=010 → x10; rd'=000 → x8; uimm[5:3]=010; uimm[2]=0; uimm[6]=0; uimm[6:0]=0010000; zero-extend(4) × 4 = 16 B; input offset is already in bytes, with no additional scaling.
Calculate
Not computed
Commit result
Pending commit
Architectural result
Architectural result not committed yet.
Quick Understanding & Search Notes
C.LW uses CL format: rs1' plus a zero-extended, 4-byte-scaled offset forms the address, and the loaded word is sign-extended to XLEN.
Both rd' and rs1' can encode only x8-x15.
The EEI determines completion or an exception for a misaligned effective address.
Common Usage Scenarios
Compressed word load
Understand this scenario with real code like «c.lw x8, 0(x10) # RV64C; x10=0x2000; EEI permits mem32[0x2000]=0xFFFFFF80 -> x8=0xFFFFFFFFFFFFFF80».
Pre-Use Checklist
Syntax Check
- Confirm RV32C / RV64C and the 16-bit encoding conditions.
- C.LW uses the 16-bit CL format; its 3-bit rd' and rs1' fields each select x8-x15.
Semantic Check
- offset is a zero-extended byte displacement from 0 through 124 in multiples of 4; the byte offset already includes the ×4 scaling.
- Base plus offset forms the effective address; a completed 32-bit load is sign-extended to XLEN and written to rd'. The EEI defines misaligned outcomes.
Pitfalls / Common Confusions
rd' and rs1' limited to x8-x15
The offset is zero-extended (not sign-extended), ranges from 0 through 124 bytes, and is scaled by 4; RV64 still sign-extends the loaded 32-bit word
For a misaligned effective address, the EEI determines whether access completes or raises address-misaligned/access-fault