Does C.LWSP zero-extend on RV64?
No. It expands to lw, so the loaded 32-bit word is sign-extended to XLEN.
C.LWSP
RISC-V C.LWSP Instruction Details
Instruction ManualC-typeLoad 32-bit word from sp+offset. CI format. rd!=x0.
Instruction Syntax
c.lwsp rd, offset(sp)
Operand Breakdown
16-bit CI format; the full 5-bit rd selects x1–x31, with rd=x0 reserved and base fixed to x2/sp.
The zero-extended byte offset is 0–252 in multiples of four; it already includes ×4 scaling.
A completed 32-bit load is sign-extended to XLEN; rd=sp uses the old sp before writeback. The EEI defines misaligned outcomes.
CCompressed Instruction
Instruction Behavior
C.LWSP uses CI format to load a 32-bit word from sp (x2) plus a zero-extended, 4-byte-scaled offset into rd. It expands to lw rd, offset(x2), so on RV64 the word is sign-extended to XLEN. It is valid only when rd is not x0; rd=x0 encodings are reserved. The offset range is 0 through 252 bytes.
C.LWSP Decode & Execute Animation
c.lwsp,(sp)
RV64I + C extension; 16-bit encoding
Assumes readable/writable ordinary memory without additional permission faults. The EEI option applies only to addresses not naturally 4-byte aligned; byte order, general permissions, device effects, and post-trap state are not modeled.
0x0000000000002000 + 16 = 0x0000000000002010 (mod 2^64) → x10 <- 0xFFFFFFFFFFFFFF80; PC+2
16-bit encoding fields
15..13
funct3
010
12
uimm[5]
0
11..7
rd
01010
6..4
uimm[4:2]
100
3..2
uimm[7:6]
00
1..0
op
10
Register mapping
rd=01010 -> x10; base=x2/sp
Immediate reconstruction
uimm[5]=0; uimm[4:2]=100; uimm[7:6]=00 -> 4 × 4 = 16 bytes (zero-extended)
Calculation
Not calculated
Access
Not accessed
Current architectural state
Not committed; registers, memory and PC retain their initial state.
Teaching stages show ISA-visible effects, not a CPU pipeline, cache, or timing model.
Quick Understanding & Search Notes
C.LWSP adds x2/sp to a 4-byte-multiple offset from 0 through 252; because it is equivalent to lw, RV64 sign-extends the loaded 32-bit value to XLEN.
The CI rd field can name any integer register, but code points with rd=x0 are reserved.
For a misaligned effective address, the EEI determines whether the access completes or raises an address-misaligned or access-fault exception.
Common Usage Scenarios
Stack Access
Understand this scenario with real code like «c.lwsp x10, 16(sp) # RV64: sp=0x2000, word at 0x2010=0xFFFFFF80 -> x10=0xFFFFFFFFFFFFFF80».
Pre-Use Checklist
Syntax Check
- Confirm RV32C / RV64C and the 16-bit encoding conditions.
- 16-bit CI format; the full 5-bit rd selects x1–x31, with rd=x0 reserved and base fixed to x2/sp.
Semantic Check
- The zero-extended byte offset is 0–252 in multiples of four; it already includes ×4 scaling.
- A completed 32-bit load is sign-extended to XLEN; rd=sp uses the old sp before writeback. The EEI defines misaligned outcomes.
Pitfalls / Common Confusions
rd=x0 encodings are reserved
on RV64 the loaded word is sign-extended, not zero-extended