Does C.LWSP zero-extend on RV64?
No. It expands to lw, so the loaded 32-bit word is sign-extended to XLEN.
C.LWSP
RISC-V C.LWSP Instruction Details
Instruction ManualC-typeLoad 32-bit word from sp+offset. CI format. rd!=x0.
Instruction Syntax
c.lwsp rd, offset(sp)
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.LWSP uses CI format to load a 32-bit word from sp (x2) plus a zero-extended, 4-byte-scaled offset into rd. It expands to lw rd, offset(x2), so on RV64 the word is sign-extended to XLEN. It is valid only when rd is not x0; rd=x0 encodings are reserved. The offset range is 0 through 252 bytes.
C.LWSP Decode & Execute Animation
Shows only RISC-V ISA-visible 16-bit encoding, operands, and state; it does not simulate a pipeline, cache, endianness implementation, or timing.
c.lwsp,(sp)
Execution context
The EEI choice affects this result only when the effective address is not divisible by 4; a naturally aligned access must not raise an address-misaligned exception.
16-bit encoding fields
15..13
funct3
010
12
uimm[5]
0
11..7
rd
01010
6..4
uimm[4:2]
100
3..2
uimm[7:6]
00
1..0
op
10
Execution data path
Address
0x0000000000002000 + 16 = 0x0000000000002010
Alignment
Naturally 4-byte aligned
Load
0xFFFFFF80 -> 0xFFFFFFFFFFFFFF80
Architectural result
x10 <- 0xFFFFFFFFFFFFFF80
Quick Understanding & Search Notes
C.LWSP adds x2/sp to a 4-byte-multiple offset from 0 through 252; because it is equivalent to lw, RV64 sign-extends the loaded 32-bit value to XLEN.
The CI rd field can name any integer register, but code points with rd=x0 are reserved.
For a misaligned effective address, the EEI determines whether the access completes or raises an address-misaligned or access-fault exception.
Common Usage Scenarios
Stack Access
Understand this scenario with real code like «c.lwsp x10, 16(sp) # x10 = *(sp+16)».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
rd=x0 encodings are reserved
on RV64 the loaded word is sign-extended, not zero-extended