RISC-V C.LWSP Instruction Details

Instruction ManualC-type

Load 32-bit word from sp+offset. CI format. rd!=x0.

Instruction Syntax

c.lwsp rd, offset(sp)

Operand Breakdown

Compressed instructions are 16 bits; registers are often limited to x8–x15.

Immediate fields are narrower. Refer to the full encoding for this compressed instruction.

CCompressed Instruction

Related Search Terms

C.LWSP instruction RISC-V C.LWSP c.lwsp syntax c.lwsp encoding c.lwsp C-type c.lwsp compressed instruction c.lwsp load

Instruction Behavior

C.LWSP (CI format, rd any of 32 registers) loads 32-bit value from sp(x2) + zero-extended offset (×4) into rd. Expands to lw rd,offset(x2). Valid only when rd≠x0. Offset range 0-252 bytes.

Common Usage Scenarios

Understand this scenario with real code like «c.lwsp x10, 16(sp) # x10 = *(sp+16)».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is C-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

rd cannot be x0