Why must a C.SWSP offset be a multiple of four?
Its compressed offset is word-scaled, forming a zero-extended byte offset multiplied by four.
C.SWSP
RISC-V C.SWSP Instruction Details
Instruction ManualC-typeStore 32-bit word to sp+offset. CSS format.
Instruction Syntax
c.swsp rs2, offset(sp)
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.SWSP uses CSS format to store the low 32 bits of rs2 to the address formed by sp (x2) plus a zero-extended, 4-byte-scaled offset. It expands to sw rs2, offset(x2), and rs2 can be any integer register. The offset range is 0 through 252 bytes.
C.SWSP Decode & Execute Animation
Shows only RISC-V ISA-visible 16-bit encoding, operands, and state; it does not simulate a pipeline, cache, endianness implementation, or timing.
c.swsp,(sp)
Execution context
The EEI choice affects this result only when the effective address is not divisible by 4; a naturally aligned access must not raise an address-misaligned exception.
16-bit encoding fields
15..13
funct3
110
12..9
uimm[5:2]
0100
8..7
uimm[7:6]
00
6..2
rs2
01010
1..0
op
10
Execution data path
Address
0x0000000000002000 + 16 = 0x0000000000002010
Alignment
Naturally 4-byte aligned
Store
0x0000000012345678 -> low 32 bits 0x12345678
Architectural result
mem[0x0000000000002010] <- 0x12345678
Quick Understanding & Search Notes
C.SWSP fixes x2/sp as its base, uses a 4-byte-multiple offset from 0 through 252, and stores the low 32 bits of rs2.
The CSS rs2 field is a full 5-bit register field, not limited to x8-x15.
A naturally aligned word access must not raise an address-misaligned exception; misaligned behavior depends on the EEI.
Common Usage Scenarios
Stack Access
Understand this scenario with real code like «c.swsp x10, 16(sp) # *(sp+16) = x10».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
rs2 can name any integer register, but only its low 32 bits are stored
the EEI determines the outcome of a misaligned effective address