Why must a C.SWSP offset be a multiple of four?
Its compressed offset is word-scaled, forming a zero-extended byte offset multiplied by four.
C.SWSP
RISC-V C.SWSP Instruction Details
Instruction ManualC-typeStore 32-bit word to sp+offset. CSS format.
Instruction Syntax
c.swsp rs2, offset(sp)
Operand Breakdown
16-bit CSS format; the full 5-bit rs2 selects x0–x31 and the base is fixed to x2/sp.
The zero-extended byte offset is 0–252 in multiples of four; it already includes ×4 scaling.
A completed access stores only rs2[31:0] without writing GPRs; rs2=sp uses the same old sp and rs2=x0 stores zero. The EEI defines misaligned outcomes.
CCompressed Instruction
Instruction Behavior
C.SWSP uses CSS format to store the low 32 bits of rs2 to the address formed by sp (x2) plus a zero-extended, 4-byte-scaled offset. It expands to sw rs2, offset(x2), and rs2 can be any integer register. The offset range is 0 through 252 bytes.
C.SWSP Decode & Execute Animation
c.swsp,(sp)
RV64I + C extension; 16-bit encoding
Assumes readable/writable ordinary memory without additional permission faults. The EEI option applies only to addresses not naturally 4-byte aligned; byte order, general permissions, device effects, and post-trap state are not modeled.
0x0000000000002000 + 16 = 0x0000000000002010 (mod 2^64) → mem[0x0000000000002010] <- 0x12345678; PC+2; general registers unchanged
16-bit encoding fields
15..13
funct3
110
12..9
uimm[5:2]
0100
8..7
uimm[7:6]
00
6..2
rs2
01010
1..0
op
10
Register mapping
rs2=01010 -> x10; base=x2/sp
Immediate reconstruction
uimm[5:2]=0100; uimm[7:6]=00 -> 4 × 4 = 16 bytes (zero-extended)
Calculation
Not calculated
Access
Not accessed
Current architectural state
Not committed; registers, memory and PC retain their initial state.
Teaching stages show ISA-visible effects, not a CPU pipeline, cache, or timing model.
Quick Understanding & Search Notes
C.SWSP fixes x2/sp as its base, uses a 4-byte-multiple offset from 0 through 252, and stores the low 32 bits of rs2.
The CSS rs2 field is a full 5-bit register field, not limited to x8-x15.
A naturally aligned word access must not raise an address-misaligned exception; misaligned behavior depends on the EEI.
Common Usage Scenarios
Stack Access
Understand this scenario with real code like «c.swsp x10, 16(sp) # sp=0x2000, x10=0x12345678 -> word at 0x2010=0x12345678».
Pre-Use Checklist
Syntax Check
- Confirm RV32C / RV64C and the 16-bit encoding conditions.
- 16-bit CSS format; the full 5-bit rs2 selects x0–x31 and the base is fixed to x2/sp.
Semantic Check
- The zero-extended byte offset is 0–252 in multiples of four; it already includes ×4 scaling.
- A completed access stores only rs2[31:0] without writing GPRs; rs2=sp uses the same old sp and rs2=x0 stores zero. The EEI defines misaligned outcomes.
Pitfalls / Common Confusions
rs2 can name any integer register, but only its low 32 bits are stored
the EEI determines the outcome of a misaligned effective address