C.SWSP
RISC-V C.SWSP Instruction Details
Instruction ManualC-typeStore 32-bit word to sp+offset. CSS format.
Instruction Syntax
c.swsp rs2, offset(sp)
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.SWSP (CSS format, rs2 any of 32 registers) stores 32-bit value of rs2 to address sp(x2) + zero-extended offset (×4). Expands to sw rs2,offset(x2). Offset range 0-252 bytes.
Common Usage Scenarios
Register Operations
Understand this scenario with real code like «c.swsp x10, 16(sp) # *(sp+16) = x10».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
no special restrictions