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C.SW

RISC-V C.SW Instruction Details

Instruction ManualC-type

Store 32-bit word to memory. CS format.

Instruction Syntax

c.sw rs2', offset(rs1')
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Related Search Terms
C.SW instructionRISC-V C.SWc.sw syntaxc.sw encodingc.sw C-typec.sw compressed instructionc.sw store

Instruction Behavior

C.SW (CS format, rs1' and rs2' x8-x15 only) stores 32-bit value of rs2' to address rs1' + zero-extended offset (×4). Expands to sw rs2',offset(rs1').

Common Usage Scenarios

Compressed & Code Size

Understand this scenario with real code like «c.sw x8, 0(x10)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is C-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

registers limited to x8-x15