Does C.SW store the whole RV64 register?
No. Like sw, it stores only the low 32 bits of rs2'.
C.SW
RISC-V C.SW Instruction Details
Instruction ManualC-typeStore 32-bit word to memory. CS format.
Instruction Syntax
c.sw rs2', offset(rs1')
Operand Breakdown
16-bit CS format; the two 3-bit rs1′ and rs2′ fields select x8–x15.
The zero-extended byte offset is 0–124 in multiples of four; it already includes ×4 scaling.
A completed access stores only rs2′[31:0] without writing GPRs; equal source and base registers share the old value. The EEI defines misaligned outcomes.
CCompressed Instruction
Instruction Behavior
C.SW uses CS format, with both rs1' and rs2' limited to x8-x15. It stores the low 32 bits of rs2' to the address formed by rs1' plus a zero-extended, 4-byte-scaled offset, and expands to sw rs2', offset(rs1').
C.SW Decode & Execute Animation
c.sw,()
RV64I + C extension; 16-bit encoding
Assumes readable/writable ordinary memory without additional permission faults. The EEI option applies only to addresses not naturally 4-byte aligned; byte order, general permissions, device effects, and post-trap state are not modeled.
0x0000000000002000 + 16 = 0x0000000000002010 (mod 2^64) → mem[0x0000000000002010] <- 0x12345678; PC+2; general registers unchanged
16-bit encoding fields
15..13
funct3
110
12..10
uimm[5:3]
010
9..7
rs1'
011
6
uimm[2]
0
5
uimm[6]
0
4..2
rs2'
010
1..0
op
00
Register mapping
rs1'=011 -> x11; rs2'=010 -> x10
Immediate reconstruction
uimm[5:3]=010; uimm[2]=0; uimm[6]=0 -> 4 × 4 = 16 bytes (zero-extended)
Calculation
Not calculated
Access
Not accessed
Current architectural state
Not committed; registers, memory and PC retain their initial state.
Teaching stages show ISA-visible effects, not a CPU pipeline, cache, or timing model.
Quick Understanding & Search Notes
C.SW maps its compressed register fields to x8-x15 and stores only the low 32 bits of rs2' at rs1' plus a 4-byte-scaled offset.
Both 3-bit rs1' and rs2' encodings map to x8-x15.
For a misaligned effective address, the EEI specifies completion or an address-misaligned/access-fault exception.
Common Usage Scenarios
Memory Store
Understand this scenario with real code like «c.sw x8, 0(x10) # x10=0x2000, x8=0x12345678 -> word at 0x2000=0x12345678».
Pre-Use Checklist
Syntax Check
- Confirm RV32C / RV64C and the 16-bit encoding conditions.
- 16-bit CS format; the two 3-bit rs1′ and rs2′ fields select x8–x15.
Semantic Check
- The zero-extended byte offset is 0–124 in multiples of four; it already includes ×4 scaling.
- A completed access stores only rs2′[31:0] without writing GPRs; equal source and base registers share the old value. The EEI defines misaligned outcomes.
Pitfalls / Common Confusions
registers limited to x8-x15