Does C.SW store the whole RV64 register?
No. Like sw, it stores only the low 32 bits of rs2'.
C.SW
RISC-V C.SW Instruction Details
Instruction ManualC-typeStore 32-bit word to memory. CS format.
Instruction Syntax
c.sw rs2', offset(rs1')
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.SW uses CS format, with both rs1' and rs2' limited to x8-x15. It stores the low 32 bits of rs2' to the address formed by rs1' plus a zero-extended, 4-byte-scaled offset, and expands to sw rs2', offset(rs1').
C.SW Decode & Execute Animation
Shows only RISC-V ISA-visible 16-bit encoding, operands, and state; it does not simulate a pipeline, cache, endianness implementation, or timing.
c.sw,()
Execution context
The EEI choice affects this result only when the effective address is not divisible by 4; a naturally aligned access must not raise an address-misaligned exception.
16-bit encoding fields
15..13
funct3
110
12..10
uimm[5:3]
010
9..7
rs1'
010
6
uimm[2]
0
5
uimm[6]
0
4..2
rs2'
010
1..0
op
00
Execution data path
Address
0x0000000000002000 + 16 = 0x0000000000002010
Alignment
Naturally 4-byte aligned
Store
0x0000000012345678 -> low 32 bits 0x12345678
Architectural result
mem[0x0000000000002010] <- 0x12345678
Quick Understanding & Search Notes
C.SW maps its compressed register fields to x8-x15 and stores only the low 32 bits of rs2' at rs1' plus a 4-byte-scaled offset.
Both 3-bit rs1' and rs2' encodings map to x8-x15.
For a misaligned effective address, the EEI specifies completion or an address-misaligned/access-fault exception.
Common Usage Scenarios
Memory Store
Understand this scenario with real code like «c.sw x8, 0(x10)».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
registers limited to x8-x15