Which extensions does C.MUL require?
Zcb requires Zca; C.MUL additionally requires M or Zmmul, on RV32/RV64.
C.MUL
RISC-V C.MUL Instruction Details
Instruction ManualC-typeZcb 16-bit multiply: multiply two signed XLEN operands and write the low XLEN product bits.
Instruction Syntax
c.mul rsd', rs2'
Operand Breakdown
RV32/RV64 Zcb requiring Zca; 16-bit CA format, also requiring M or Zmmul.
Three-bit rd'/rs1' and rs2' select x8–x15; the destination is also the first source.
No immediate: compute the signed product and write only its low XLEN bits, discarding high bits.
Overlapping sources read the same pre-writeback value; x0 is outside the encodable register subset.
ZcbCompressed Instruction
Instruction Behavior
C.MUL (Zcb, CA format) multiplies rsd' and rs2' as signed XLEN values and writes the low XLEN product bits to rsd'. Both compressed registers are x8-x15; Zcb depends on Zca, and M or Zmmul must also be configured.
C.MUL Decode & Execute Animation
Shows only ISA-visible 16-bit encoding, operands, and state, not a pipeline, cache, or timing.
c.mul,
Execution context
x10 <- 0xFFFFFFFD * 0x00000007 = 0xFFFFFFEB
16-bit encoding fields
15..10
funct6
100111
9..7
rd'/rs1'
010
6..5
funct2
10
4..2
rs2'
011
1..0
op
01
Execution data path
Compressed operand mapping
rd'/rs1'=010 -> x(8+2)=x10, rs2'=011 -> x(8+3)=x11; read values before writeback
Concrete calculation
The Calculate stage shows the equation for the current inputs.
Architectural result
Continue to Commit result to reveal architectural state.
Quick Understanding & Search Notes
C.MUL's two CA compressed-register fields map to x8-x15; the result retains only the low XLEN bits of the signed product.
C.MUL has no immediate; rsd' is read/write and rs2' is the second source operand.
It is defined only when Zcb and either M or Zmmul are available.
Common Usage Scenarios
Compressed integer arithmetic
RV32 Zcb+Zca+M/Zmmul, x10=-3 and x11=7: c.mul x10, x11 writes x10=0xffffffeb, the low 32 bits of -21.
Pre-Use Checklist
Syntax Check
- RV32/RV64 Zcb requiring Zca; 16-bit CA format, also requiring M or Zmmul.
- Three-bit rd'/rs1' and rs2' select x8–x15; the destination is also the first source.
Semantic Check
- No immediate: compute the signed product and write only its low XLEN bits, discarding high bits.
- Overlapping sources read the same pre-writeback value; x0 is outside the encodable register subset.
Pitfalls / Common Confusions
Requires M or Zmmul
rd' and rs2' limited to x8-x15
Only low XLEN bits of product (truncated)
FAQ
Are the high product bits retained?
No: only the low XLEN bits are written. rsd' is read/write; both registers are x8–x15.