Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.MUL
RISC-V C.MUL Instruction Details
Instruction ManualC-typeZcb 16-bit multiply: multiply two signed XLEN operands and write the low XLEN product bits.
Instruction Syntax
c.mul rsd', rs2'
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcbCompressed Instruction
Instruction Behavior
C.MUL (Zcb, CA format) multiplies rsd' and rs2' as signed XLEN values and writes the low XLEN product bits to rsd'. Both compressed registers are x8-x15; Zcb depends on Zca, and M or Zmmul must also be configured.
C.MUL Decode & Execute Animation
Shows only ISA-visible 16-bit encoding, operands, and state, not a pipeline, cache, or timing.
c.mul,
Execution context
x10 <- 0xFFFFFFFD * 0x00000007 = 0xFFFFFFEB
16-bit encoding fields
15..10
funct6
100111
9..7
rd'/rs1'
010
6..5
funct2
10
4..2
rs2'
011
1..0
op
01
Execution data path
Input to result
x10 <- 0xFFFFFFFD * 0x00000007 = 0xFFFFFFEB
Concrete calculation
The Calculate stage shows the equation for the current inputs.
Architectural state
Architectural state is written only at Commit result.
Architectural result
Continue to Commit result to reveal architectural state.
Quick Understanding & Search Notes
C.MUL's two CA compressed-register fields map to x8-x15; the result retains only the low XLEN bits of the signed product.
C.MUL has no immediate; rsd' is read/write and rs2' is the second source operand.
It is defined only when Zcb and either M or Zmmul are available.
Common Usage Scenarios
Compressed integer arithmetic
Understand this scenario with real code like «c.mul x10, x11 # x10 = (x10 * x11)[XLEN-1:0]».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
Requires M or Zmmul
rd' and rs2' limited to x8-x15
Only low XLEN bits of product (truncated)
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.