Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.MUL
RISC-V C.MUL Instruction Details
Instruction ManualC-type16-bit encoding of mul, low XLEN bits of product
Instruction Syntax
c.mul rsd', rs2'
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcbCompressed Instruction
Instruction Behavior
C.MUL (Zcb, CA format) multiplies rsd' and rs2', writes low XLEN bits to rsd'. rd' and rs2' limited to x8-x15. Requires M or Zmmul. Expands to mul rsd',rsd',rs2'. Part of Zcb, depends on Zca and M/Zmmul.
Quick Understanding & Search Notes
C.MUL is the 16-bit encoding form for compressed multiply; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Arrays & Memory Access
Understand this scenario with real code like «c.mul x10, x11 # x10 = (x10 * x11)[XLEN-1:0]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Requires M or Zmmul
rd' and rs2' limited to x8-x15
Only low XLEN bits of product (truncated)
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.