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C.NOT

RISC-V C.NOT Instruction Details

Instruction ManualC-type

16-bit bitwise NOT (one's complement)

Instruction Syntax

c.not rsd'
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcbCompressed Instruction
Related Search Terms
C.NOT instructionRISC-V C.NOTc.not syntaxc.not encodingc.not Zcbc.not compressed instructioncompressed bitwise NOT

Instruction Behavior

C.NOT (Zcb, CU format) performs bitwise NOT on rsd' (XOR with -1). rsd' limited to x8-x15. Expands to xori rd',rd',-1. Part of Zcb, depends on Zca.

C.NOT Decode & Execute Animation

Shows only ISA-visible 16-bit encoding, operands, and state, not a pipeline, cache, or timing.

c.not
Execution context
x10 <- ~0x00FF00FF = 0xFF00FF00
16-bit encoding fields
15..10
funct6
100111
9..7
rd'/rs1'
010
6..5
funct2
11
4..2
C.NOT
101
1..0
op
01
Execution data path
Input to result
x10 <- ~0x00FF00FF = 0xFF00FF00
Concrete calculation
The Calculate stage shows the equation for the current inputs.
Architectural state
Architectural state is written only at Commit result.
Architectural result

Continue to Commit result to reveal architectural state.

Quick Understanding & Search Notes

C.NOT's single rd'/rs1' field maps to x8-x15 and computes XOR with -1 in that same register.

C.NOT has neither an immediate nor a second source register; its only operand is both source and destination.
Zcb depends on Zca; this C.NOT has no additional M, Zbb, or XLEN prerequisite.
RISC-V Unprivileged ISA Manual, Zc Extensions

Common Usage Scenarios

Compressed integer bit operations

Understand this scenario with real code like «c.not x10 # x10 = ~x10».

Pre-Use Checklist

Syntax Check
  • Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
  • Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
  • Note the limited operand space of compressed instructions.
  • Verify this compressed instruction has a corresponding 32-bit expansion.

Pitfalls / Common Confusions

Operand limited to x8-x15
Equivalent to xori rd', rd', -1

FAQ

Is it always equivalent to a same-named 32-bit instruction?

Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.

Why do register restrictions matter?

Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.