Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.SB
RISC-V C.SB Instruction Details
Instruction ManualC-type16-bit encoding of sb, store least significant byte
Instruction Syntax
c.sb rs2', uimm(rs1')
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcbCompressed Instruction
Instruction Behavior
C.SB (Zcb, CSB format) stores LSB of rs2' to address rs1' + zero-extended offset. rs1' and rs2' limited to x8-x15. Expands to sb rs2',uimm(rs1'). Offset is 2-bit unsigned. Part of Zcb, depends on Zca.
C.SB Decode & Execute Animation
Shows only ISA-visible 16-bit encoding, operands, and state, not a pipeline, cache, or timing.
c.sb,()
Execution context
x10 + 3 -> mem[0x00002003] <- 0xAB
16-bit encoding fields
15..10
funct6
100010
9..7
rs1'
010
6..5
uimm[0|1]
11
4..2
rs2'
001
1..0
op
00
Execution data path
Input to result
x10 + 3 -> mem[0x00002003] <- 0xAB
Concrete calculation
The Calculate stage shows the equation for the current inputs.
Architectural state
Architectural state is written only at Commit result.
Architectural result
Continue to Commit result to reveal architectural state.
Quick Understanding & Search Notes
C.SB uses the CSB format: rs1' and rs2' map to x8-x15, and uimm[1:0] is a zero-extended byte offset.
uimm[1] comes from encoding bit 5 and uimm[0] from bit 6; it is not scaled by the access width.
Only the low byte of rs2' is stored; a byte access cannot raise an address-misaligned exception.
Common Usage Scenarios
Arrays & Memory Access
Understand this scenario with real code like «c.sb x9, 3(x10) # store byte».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
rs1' and rs2' limited to x8-x15
Offset is 2-bit unsigned (0-3 bytes)
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.