How is the C.SB offset encoded?
Byte offset 0–3: bit5 supplies uimm[1], bit6 supplies uimm[0]; zero-extend without scaling.
C.SB
RISC-V C.SB Instruction Details
Instruction ManualC-type16-bit encoding of sb, store least significant byte
Instruction Syntax
c.sb rs2', uimm(rs1')
Operand Breakdown
RV32/RV64 Zcb requiring Zca; 16-bit CSB format. C alone does not provide this instruction.
Three-bit rs1'/rs2' fields select x8–x15; the byte offset is 0–3.
uimm[1:0]={inst[5],inst[6]}, zero-extended without scaling; add the byte offset to the base.
Completion stores only the low eight bits of rs2'. Byte accesses are naturally aligned, but EEI access rules apply.
ZcbCompressed Instruction
Instruction Behavior
C.SB (Zcb, CSB format) stores the low byte of rs2' to address rs1' + zero-extended offset. rs1' and rs2' limited to x8-x15. Expands to sb rs2',uimm(rs1'). Offset is 2-bit unsigned. Part of Zcb, depends on Zca.
C.SB Decode & Execute Animation
Shows only ISA-visible 16-bit encoding, operands, and state, not a pipeline, cache, or timing.
c.sb,()
Execution context
0x00002000 + 3 (mod 2^32) -> 0x00002003; mem8 <- 0xAB
16-bit encoding fields
15..10
funct6
100010
9..7
rs1'
010
6..5
uimm[0|1]
11
4..2
rs2'
001
1..0
op
00
Execution data path
Compressed operand mapping
rs1'=010 -> x(8+2)=x10, rs2'=001 -> x(8+1)=x9; uimm[1:0]={inst[5],inst[6]}=11 -> zero-extended byte offset 3
Concrete calculation
The Calculate stage shows the equation for the current inputs.
Architectural result
Continue to Commit result to reveal architectural state.
Quick Understanding & Search Notes
C.SB uses the CSB format: rs1' and rs2' map to x8-x15, and uimm[1:0] is a zero-extended byte offset.
uimm[1] comes from encoding bit 5 and uimm[0] from bit 6; it is not scaled by the access width.
Only the low byte of rs2' is stored; a byte access cannot raise an address-misaligned exception.
Common Usage Scenarios
Arrays & Memory Access
RV32/RV64 Zcb+Zca, x10=0x2000 and x9=0x123456ab: c.sb x9, 3(x10), on completion, writes mem8[0x2003]=0xab.
Pre-Use Checklist
Syntax Check
- RV32/RV64 Zcb requiring Zca; 16-bit CSB format. C alone does not provide this instruction.
- Three-bit rs1'/rs2' fields select x8–x15; the byte offset is 0–3.
Semantic Check
- uimm[1:0]={inst[5],inst[6]}, zero-extended without scaling; add the byte offset to the base.
- Completion stores only the low eight bits of rs2'. Byte accesses are naturally aligned, but EEI access rules apply.
Pitfalls / Common Confusions
rs1' and rs2' limited to x8-x15
Offset is 2-bit unsigned (0-3 bytes)
FAQ
Can a byte store raise an alignment exception?
Every byte address is naturally aligned, so no address-misaligned exception; EEI access rules still apply.