Which source-register bits does C.SH store?
It writes the least-significant 16 bits of rs2' to memory; higher source-register bits do not contribute to the stored value.
C.SH
RISC-V C.SH Instruction Details
Instruction ManualC-type16-bit encoding of sh, store lower 16 bits
Instruction Syntax
c.sh rs2', uimm(rs1')
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcbCompressed Instruction
Instruction Behavior
C.SH uses the Zcb CSH format. It stores the low 16 bits of rs2' at rs1' plus zero-extended uimm. Both rs1' and rs2' map to x8-x15; uimm[1] comes from encoding bit 5 and uimm[0] is zero, so the offset is only 0 or 2.
C.SH Decode & Execute Animation
Shows only official 16-bit fields, operands, conditions, and architectural state; it does not model a pipeline, cache, or timing.
c.sh,()
Execution context
A naturally aligned access cannot raise an address-misaligned exception; any address can still raise an access-fault according to the EEI's access rules.
mem[0x00002002] <- 0xABCD
16-bit encoding fields
15..10
funct6
100011
9..7
rs1'
010
6
0
0
5
uimm[1]
1
4..2
rs2'
001
1..0
op
00
Execution data path
CSH fields: rs1'=x10, rs2'=x9, each maps from three bits to x8-x15; uimm=2.
0x00002000 + 2 = 0x00002002; X(x9)[15:0] = 0xABCD
mem[0x00002002][15:0] <- 0xABCD
Architectural state has not been committed.
Quick Understanding & Search Notes
C.SH maps compact rs1'/rs2' to x8-x15, reconstructs uimm of 0 or 2, and commits only rs2''s low 16 bits to the effective address.
CSH rs1' and rs2' are three-bit fields mapping to x8-x15 as the base and store source.
uimm[31:2] is zero, uimm[1] is encoding[5], and uimm[0] is zero; the operation is mem[X(rs1')+EXTZ(uimm)][15:0] = X(rs2').
Common Usage Scenarios
Compact halfword stores
Understand this scenario with real code like «c.sh x9, 2(x10) # store halfword».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
rs1' and rs2' limited to x8-x15
uimm is only 0 or 2 bytes; whether the effective address is misaligned still depends on rs1' and the EEI.
FAQ
Which offsets can C.SH encode?
uimm[1] comes from encoding bit 5 and uimm[0] is fixed to zero, so the zero-extended offset can only be 0 or 2 bytes.