Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.SH
RISC-V C.SH Instruction Details
Instruction ManualC-type16-bit encoding of sh, store lower 16 bits
Instruction Syntax
c.sh rs2', uimm(rs1')
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcbCompressed Instruction
Instruction Behavior
C.SH (Zcb, CSH format) stores lower 16 bits of rs2' to address rs1' + zero-extended offset. rs1' and rs2' limited to x8-x15. Expands to sh rs2',uimm(rs1'). Offset is 1-bit unsigned ×2. Part of Zcb, depends on Zca.
Quick Understanding & Search Notes
C.SH is the 16-bit encoding form for compressed halfword store; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Arrays & Memory Access
Understand this scenario with real code like «c.sh x9, 2(x10) # store halfword».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
rs1' and rs2' limited to x8-x15
Offset only 1-bit unsigned (0 or 2 bytes)
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.