Which source-register bits does C.SH store?
It writes the least-significant 16 bits of rs2' to memory; higher source-register bits do not contribute to the stored value.
C.SH
RISC-V C.SH Instruction Details
Instruction ManualC-type16-bit encoding of sh, store lower 16 bits
Instruction Syntax
c.sh rs2', uimm(rs1')
Operand Breakdown
RV32/RV64 Zcb requiring Zca; 16-bit CSH format, with no additional Zbb prerequisite.
Three-bit rs1'/rs2' select x8–x15 for base and source; overlapping operands read the same register value.
uimm[1:0]={inst[5],0}, a zero-extended byte offset of 0 or 2; do not scale it again before adding the base.
Completion stores only the low 16 source bits; misaligned outcomes depend on the EEI and faults may follow partial writes.
ZcbCompressed Instruction
Extension condition: RV32/RV64 Zcb, requiring Zca; no additional Zbb prerequisite.
Instruction Behavior
C.SH uses the Zcb CSH format. It stores the low 16 bits of rs2' at rs1' plus zero-extended uimm. Both rs1' and rs2' map to x8-x15; uimm[1] comes from encoding bit 5 and uimm[0] is zero, so the offset is only 0 or 2.
C.SH Decode & Execute Animation
Shows only official 16-bit fields, operands, conditions, and architectural state; it does not model a pipeline, cache, or timing.
c.sh,()
Execution context
RV32/RV64 Zcb + Zca
A naturally aligned access cannot raise an address-misaligned exception; any address can still raise an access-fault according to the EEI's access rules.
0x00002000 + 2 → mem[0x00002002] <- 0xABCD
16-bit encoding fields
15..10
funct6
100011
9..7
rs1'
010
6
0
0
5
uimm[1]
1
4..2
rs2'
001
1..0
op
00
Execution data path
CSH fields: rs1'=010→x10, rs2'=001→x9, each maps from three bits to x8-x15; uimm=2.
uimm={inst[5],0}=10=2; EXTZ(uimm)
0x00002000 + 2 = 0x00002002; X(x9)[15:0] = 0xABCD
mem[0x00002002][15:0] <- 0xABCD
Architectural state has not been committed.
Quick Understanding & Search Notes
C.SH maps compact rs1′/rs2′ to x8–x15 and reconstructs a byte offset of 0 or 2; a completed access stores the low 16 source bits.
CSH rs1' and rs2' are three-bit fields mapping to x8-x15 as the base and store source.
uimm[31:2] is zero, uimm[1] is encoding[5], and uimm[0] is zero; the operation is mem[X(rs1')+EXTZ(uimm)][15:0] = X(rs2').
Naturally aligned addresses cannot raise address-misaligned exceptions. The EEI defines completion or traps for misaligned accesses; faults may follow partial writes.
Common Usage Scenarios
Compact halfword stores
RV32/RV64 Zcb+Zca, x10=0x2000 and x9=0x1234abcd: c.sh x9, 2(x10) writes mem16[0x2002]=0xabcd on completion.
Pre-Use Checklist
Syntax Check
- RV32/RV64 Zcb requiring Zca; 16-bit CSH format, with no additional Zbb prerequisite.
- Three-bit rs1'/rs2' select x8–x15 for base and source; overlapping operands read the same register value.
Semantic Check
- uimm[1:0]={inst[5],0}, a zero-extended byte offset of 0 or 2; do not scale it again before adding the base.
- Completion stores only the low 16 source bits; misaligned outcomes depend on the EEI and faults may follow partial writes.
Pitfalls / Common Confusions
rs1' and rs2' limited to x8-x15
uimm is only 0 or 2 bytes; whether the effective address is misaligned still depends on rs1' and the EEI.
FAQ
Which offsets can C.SH encode?
uimm[1] comes from encoding bit 5 and uimm[0] is fixed to zero, so the zero-extended offset can only be 0 or 2 bytes.