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C.ZEXT.B

RISC-V C.ZEXT.B Instruction Details

Instruction ManualC-type

16-bit zero-extend byte (least-significant 8 bits)

Instruction Syntax

c.zext.b rd'/rs1'
Operand Breakdown
RV32/RV64 Zcb, requiring Zca with no further extension prerequisite; 16-bit CU format.
The sole three-bit rd'/rs1' field selects x8-x15, reading and writing one register; no immediate.
Keep the low 8 bits and clear all higher bits, writing the same register.
ZcbCompressed Instruction

Extension condition: RV32/RV64; Zcb requires Zca; no further extension prerequisite.

Related Search Terms
C.ZEXT.B instructionRISC-V C.ZEXT.Bc.zext.b syntaxc.zext.b encodingc.zext.b Zcbc.zext.b compressed instructioncompressed zero-extend byte

Instruction Behavior

C.ZEXT.B uses CU format to zero-extend the least-significant 8 bits of its single source/destination register to XLEN. Its three-bit field selects only x8-x15. Zcb requires Zca; no further extension is required. It is equivalent to andi rd', rd', 0xff.

C.ZEXT.B Decode & Execute Animation

Shows only official 16-bit fields, conditions, and architectural state; it does not model a pipeline, cache, or timing.

c.zext.b
Execution context

C.ZEXT.B is in Zcb; Zcb depends on Zca.

x10 <- 0x00000080
16-bit encoding fields
15..10
funct6
100111
9..7
rd'/rs1'
010
6..5
funct2
11
4..2
C.ZEXT.B
000
1..0
op
01
Execution data path
CU fields restore the single rd'/rs1' field to x10; it is both the source and destination.
EXTZ(0x12345680[7:0]) = 0x00000080
x10 <- 0x00000080
Architectural state has not been committed.

Quick Understanding & Search Notes

C.ZEXT.B zero-extends rsd'[7:0] to XLEN and writes the same x8-x15 register; it is in Zcb, which depends on Zca.

CU rd'/rs1' at inst[9:7] maps to x8-x15; there is no immediate.
Keep the low 8 bits and clear all higher bits; available on RV32/RV64.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Zc* v1.0.0

Common Usage Scenarios

Zero Extension

RV32/RV64 Zcb+Zca, x10=0x12345680: c.zext.b x10 yields x10=0x80 with zero upper bits.

Pre-Use Checklist

Syntax Check
  • RV32/RV64 Zcb, requiring Zca with no further extension prerequisite; 16-bit CU format.
  • The sole three-bit rd'/rs1' field selects x8-x15, reading and writing one register; no immediate.
Semantic Check
  • Keep the low 8 bits and clear all higher bits, writing the same register.

Pitfalls / Common Confusions

Operand limited to x8-x15
Equivalent to andi rd', rd', 0xFF

FAQ

Does it read two registers?

No. rd'/rs1' denotes one x8-x15 register used for both reading and writeback.

Which extensions are required?

Zcb requires Zca; no further extension prerequisite.