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C.ZEXT.H

RISC-V C.ZEXT.H Instruction Details

Instruction ManualC-type

16-bit zero-extend halfword (lower 16 bits)

Instruction Syntax

c.zext.h rsd'
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcbZbbCompressed Instruction
Related Search Terms
C.ZEXT.H instructionRISC-V C.ZEXT.Hc.zext.h syntaxc.zext.h encodingc.zext.h Zcbc.zext.h compressed instructioncompressed zero-extend halfword

Instruction Behavior

C.ZEXT.H is a CU-format Zcb instruction that zero-extends rsd'[15:0] to XLEN; rsd' is limited to x8-x15. It also requires Zbb, and Zcb depends on Zca.

C.ZEXT.H Decode & Execute Animation

Shows only official 16-bit fields, conditions, and architectural state; it does not model a pipeline, cache, or timing.

c.zext.h
Execution context

C.ZEXT.H requires Zcb and Zbb; Zcb depends on Zca.

x10 <- 0x00008000
16-bit encoding fields
15..10
funct6
100111
9..7
rd'/rs1'
010
6..5
funct2
11
4..2
C.ZEXT.H
010
1..0
op
01
Execution data path
CU fields restore the single rd'/rs1' field to x10; it is both the source and destination.
EXTZ(X(x10)[15:0]) = 0x00008000
x10 <- 0x00008000
Architectural state has not been committed.

Quick Understanding & Search Notes

C.ZEXT.H zero-extends rsd'[15:0] and writes the same x8-x15 register; it requires Zcb and Zbb.

The single CU rd'/rs1' field supplies the low-halfword source and the writeback destination.
Zcb depends on Zca, and C.ZEXT.H additionally requires Zbb.
RISC-V Unprivileged ISA Manual, Zc Extensions

Common Usage Scenarios

Arrays & Memory Access

Understand this scenario with real code like «c.zext.h x10 # x10 = EXTZ(x10[15:0])».

Pre-Use Checklist

Syntax Check
  • Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
  • Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
  • Note the limited operand space of compressed instructions.
  • Verify this compressed instruction has a corresponding 32-bit expansion.

Pitfalls / Common Confusions

Requires Zbb
Operand limited to x8-x15
Upper XLEN-16 bits zeroed

FAQ

Is it always equivalent to a same-named 32-bit instruction?

Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.

Why do register restrictions matter?

Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.