Does it read two registers?
No. rd'/rs1' denotes one x8-x15 register used for both reading and writeback.
C.ZEXT.H
RISC-V C.ZEXT.H Instruction Details
Instruction ManualC-type16-bit zero-extend halfword (lower 16 bits)
Instruction Syntax
c.zext.h rd'/rs1'
Operand Breakdown
RV32/RV64 Zcb, requiring Zca and additionally Zbb; 16-bit CU format.
The sole three-bit rd'/rs1' field selects x8-x15, reading and writing one register; no immediate.
Keep the low 16 bits and clear all higher bits, writing the same register.
ZcbZbbCompressed Instruction
Extension condition: RV32/RV64; Zcb requires Zca; this instruction also requires Zbb.
Instruction Behavior
C.ZEXT.H uses CU format to zero-extend the least-significant 16 bits of its single source/destination register to XLEN. Its three-bit field selects only x8-x15. Zcb requires Zca; this instruction also requires Zbb.
C.ZEXT.H Decode & Execute Animation
Shows only official 16-bit fields, conditions, and architectural state; it does not model a pipeline, cache, or timing.
c.zext.h
Execution context
C.ZEXT.H requires Zcb and Zbb; Zcb depends on Zca.
x10 <- 0x00008000
16-bit encoding fields
15..10
funct6
100111
9..7
rd'/rs1'
010
6..5
funct2
11
4..2
C.ZEXT.H
010
1..0
op
01
Execution data path
CU fields restore the single rd'/rs1' field to x10; it is both the source and destination.
EXTZ(0x12348000[15:0]) = 0x00008000
x10 <- 0x00008000
Architectural state has not been committed.
Quick Understanding & Search Notes
C.ZEXT.H zero-extends rsd'[15:0] and writes the same x8-x15 register; it requires Zcb and Zbb.
CU rd'/rs1' at inst[9:7] maps to x8-x15; there is no immediate.
Keep the low 16 bits and clear all higher bits; available on RV32/RV64.
Common Usage Scenarios
Zero Extension
RV32/RV64 Zcb+Zca+Zbb, x10=0x12348000: c.zext.h x10 yields x10=0x8000 with zero upper bits.
Pre-Use Checklist
Syntax Check
- RV32/RV64 Zcb, requiring Zca and additionally Zbb; 16-bit CU format.
- The sole three-bit rd'/rs1' field selects x8-x15, reading and writing one register; no immediate.
Semantic Check
- Keep the low 16 bits and clear all higher bits, writing the same register.
Pitfalls / Common Confusions
Requires Zbb
Operand limited to x8-x15
Upper XLEN-16 bits zeroed
FAQ
Which extensions are required?
Zcb requires Zca; this instruction also requires Zbb.