Why cannot ADDIW with zero replace it?
C.ZEXT.W zero-extends the low 32 bits; ADDIW/C.ADDIW with zero sign-extends bit 31. Low bits 0x80000001 give 0x0000000080000001 and 0xffffffff80000001, respectively.
C.ZEXT.W
RISC-V C.ZEXT.W Instruction Details
Instruction ManualC-type16-bit zero-extend word (RV64: lower 32 bits)
Instruction Syntax
c.zext.w rd'/rs1'
Operand Breakdown
RV64 Zcb+Zba; Zcb depends on Zca. The 16-bit CU format has one rd'/rs1' field selecting the same x8-x15 source/destination.
rd'/rs1' encodes the register number minus 8; no immediate, and bits[4:2]=100.
Zero-extend the old low 32 bits to 64 bits, equivalent to add.uw rd', rd', zero.
ADDIW/C.ADDIW with zero sign-extends and cannot replace this zero-extension.
ZcbCompressed Instruction
Instruction Behavior
C.ZEXT.W (Zcb, CU format, RV64 only) zero-extends the low 32 bits of rd'/rs1' to 64 bits, with rd'/rs1' limited to x8-x15. It requires Zba and is equivalent to the 32-bit encoding add.uw rd', rd', zero. ADDIW/C.ADDIW with zero performs 32-bit sign-extension, not zero-extension. It belongs to Zcb and depends on Zca and Zba.
C.ZEXT.W Decode & Execute Animation
Shows only official compressed fields, conditions, and architectural state; it does not model a pipeline, cache, or timing.
c.zext.w
Execution context
C.ZEXT.W requires Zcb, Zba, and RV64; Zcb depends on Zca.
c.zext.w a0 → a0 <- 0x0000000080000001
16-bit encoding fields
15..13
funct3
100
12..10
fixed
111
9..7
rd'/rs1'
010
6..5
funct2
11
4..2
C.ZEXT.W
100
1..0
op
01
Execution data path
CU rd'/rs1'=010 restores a0 (x10); it is both source and destination.
EXTZ(0xFFFFFFFF80000001[31:0]) = 0x0000000080000001
a0 <- 0x0000000080000001
Architectural state has not been committed.
Quick Understanding & Search Notes
C.ZEXT.W is the 16-bit encoding form for compressed zero-extend word; its semantics and encodable register restriction are defined by the official Zcb rules.
The official equivalent operation for C.ZEXT.W is add.uw rd, rd, zero, used for zero-extending the low 32 bits.
ADDIW/C.ADDIW +0 is a sign-extension contrast, not an implementation of zext.w.
Common Usage Scenarios
Register Operations
RV64 Zcb+Zba, old x10=0xffffffff80000001: c.zext.w x10 writes x10=0x0000000080000001.
Compressed & Code Size
RV64 Zcb+Zba, old x10=0xffffffff80000001: c.zext.w x10 writes x10=0x0000000080000001.
Pre-Use Checklist
Syntax Check
- RV64 Zcb+Zba; Zcb depends on Zca. The 16-bit CU format has one rd'/rs1' field selecting the same x8-x15 source/destination.
- rd'/rs1' encodes the register number minus 8; no immediate, and bits[4:2]=100.
Semantic Check
- Zero-extend the old low 32 bits to 64 bits, equivalent to add.uw rd', rd', zero.
- ADDIW/C.ADDIW with zero sign-extends and cannot replace this zero-extension.
Pitfalls / Common Confusions
RV64 only.
Requires Zba and corresponds to add.uw rd, rd, zero.
Do not describe ADDIW/C.ADDIW +0 as zero-extension; that is 32-bit sign-extension.
Operand limited to x8-x15; upper 32 bits are cleared.
FAQ
Which registers and extensions are required?
RV64 only, with one x8-x15 source/destination. Requires Zcb and Zba; Zcb depends on Zca.