Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.ZEXT.W
RISC-V C.ZEXT.W Instruction Details
Instruction ManualC-type16-bit zero-extend word (RV64: lower 32 bits)
Instruction Syntax
c.zext.w rd'/rs1'
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcbCompressed Instruction
Instruction Behavior
C.ZEXT.W (Zcb, CU format, RV64 only) zero-extends the low 32 bits of rd'/rs1' to 64 bits, with rd'/rs1' limited to x8-x15. It requires Zba and is equivalent to the 32-bit encoding add.uw rd', rd', zero. ADDIW/C.ADDIW with zero performs 32-bit sign-extension, not zero-extension. It belongs to Zcb and depends on Zca and Zba.
C.ZEXT.W Decode & Execute Animation
Shows only official compressed fields, conditions, and architectural state; it does not model a pipeline, cache, or timing.
c.zext.w
Execution context
C.ZEXT.W requires Zcb, Zba, and RV64; Zcb depends on Zca.
a0 <- 0x0000000080000001
16-bit encoding fields
15..13
funct3
100
12..10
fixed
111
9..7
rd'/rs1'
010
6..5
funct2
11
4..2
C.ZEXT.W
000
1..0
op
01
Execution data path
The CU rd'/rs1' three-bit field restores a0; it is both source and destination.
EXTZ(X(a0)[31:0]) = 0x0000000080000001
a0 <- 0x0000000080000001
Architectural state has not been committed.
Quick Understanding & Search Notes
C.ZEXT.W is the 16-bit encoding form for compressed zero-extend word; its semantics and encodable register restriction are defined by the official Zcb rules.
The official equivalent operation for C.ZEXT.W is add.uw rd, rd, zero, used for zero-extending the low 32 bits.
ADDIW/C.ADDIW +0 is a sign-extension contrast, not an implementation of zext.w.
Common Usage Scenarios
Register Operations
Understand this scenario with real code like «c.zext.w x10 # x10 = EXTZ(x10[31:0]) (RV64)».
Compressed & Code Size
Understand this scenario with real code like «c.zext.w x10 # x10 = EXTZ(x10[31:0]) (RV64)».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
RV64 only.
Requires Zba and corresponds to add.uw rd, rd, zero.
Do not describe ADDIW/C.ADDIW +0 as zero-extension; that is 32-bit sign-extension.
Operand limited to x8-x15; upper 32 bits are cleared.
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.