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C.ZEXT.W

RISC-V C.ZEXT.W Instruction Details

Instruction ManualC-type

16-bit zero-extend word (RV64: lower 32 bits)

Instruction Syntax

c.zext.w rsd'
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcbCompressed Instruction
Related Search Terms
C.ZEXT.W instructionRISC-V C.ZEXT.Wc.zext.w syntaxc.zext.w encodingc.zext.w Zcbc.zext.w compressed instructioncompressed zero-extend word

Instruction Behavior

C.ZEXT.W (Zcb, CU format, RV64 only) zero-extends the low 32 bits of rsd' to 64 bits, with rsd' limited to x8-x15. It requires Zba and is equivalent to the 32-bit encoding add.uw rd', rd', zero. ADDIW/C.ADDIW with zero performs 32-bit sign-extension, not zero-extension. It belongs to Zcb and depends on Zca and Zba.

Quick Understanding & Search Notes

C.ZEXT.W is the 16-bit encoding form for compressed zero-extend word; its semantics and encodable register/immediate ranges must be read from the official C extension rules.

The official equivalent operation for C.ZEXT.W is add.uw rd, rd, zero, used for zero-extending the low 32 bits.
ADDIW/C.ADDIW +0 is a sign-extension contrast, not an implementation of zext.w.
RISC-V Unprivileged ISA Manual, Zc Extensions

Common Usage Scenarios

Arrays & Memory Access

Understand this scenario with real code like «c.zext.w x10 # x10 = EXTZ(x10[31:0]) (RV64)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is C-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

RV64 only.
Requires Zba and corresponds to add.uw rd, rd, zero.
Do not describe ADDIW/C.ADDIW +0 as zero-extension; that is 32-bit sign-extension.
Operand limited to x8-x15; upper 32 bits are cleared.

FAQ

Is it always equivalent to a same-named 32-bit instruction?

Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.

Why do register restrictions matter?

Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.