What unit is the FLH offset in?
The offset is a byte offset encoded as a signed 12-bit immediate.
FLH
RISC-V FLH Instruction Details
Instruction ManualI-typeLoad a 2-byte half-precision floating-point value from memory.
Instruction Syntax
flh rd, offset(rs1)
Operand Breakdown
rd: destination floating-point register.
rs1: integer base-address register.
offset: signed 12-bit byte offset added to rs1 to form the effective address.
ZfhZfhminFloating-Point Load
Instruction Encoding
31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
FLH uses opcode 0000111 (0x07), funct3 001. The rs1 field selects the integer base register, the immediate provides a byte offset, and rd selects the destination floating-point register.
Format: I-type
opcode: 0000111 (0x07)
funct3: 001 (0x1)
Instruction Behavior
FLH forms the effective address by adding a sign-extended 12-bit offset to x[rs1] and loads a 2-byte half-precision floating-point encoding from memory into f[rd]. Naturally aligned accesses have the architectural atomicity guarantee; misaligned behavior depends on the execution environment.
Quick Understanding & Search Notes
FLH is a half-precision memory instruction between floating-point registers and memory. Address calculation uses base plus signed 12-bit byte offset, like integer load/store instructions.
The access width is 2 bytes; strict alignment and misaligned handling depend on the execution environment.
The loaded result is represented in that floating format and NaN-boxed in a wider FLEN register.
Common Usage Scenarios
Floating-Point Memory
Understand this scenario with real code like «flh f10, 0(x11) ; load half-precision from [x11]».
Data Load/Store
Understand this scenario with real code like «flh f10, 0(x11) ; load half-precision from [x11]».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register.
- rs1: integer base-address register.
- offset: signed 12-bit byte offset added to rs1 to form the effective address.
Semantic Check
- Confirm offset is a byte offset, not an element index.
- Check natural alignment and the execution environment's misaligned-access rules.
Pitfalls / Common Confusions
offset is a signed 12-bit byte offset, not an element index.
The architectural atomicity guarantee applies to naturally aligned accesses; misaligned support is execution-environment-defined.
Loading a narrower format into a wider FLEN register follows NaN-boxing rules.
FAQ
Does FLH convert floating-point formats?
No. Memory instructions move the encoding bits for that format; use FCVT for format conversion.