Is rs1 in FLH an FP register?
No. rs1 is an integer register that provides the memory base address; rd is the FP destination register.
FLH
RISC-V FLH Instruction Details
Instruction ManualI-typeLoad a 16-bit half-precision floating-point bit pattern from memory into an FP register.
Instruction Syntax
flh rd, offset(rs1)
Operand Breakdown
rd: destination floating-point register.
rs1: integer base-address register.
offset: signed 12-bit byte offset added to rs1 to form the effective address.
ZfhZfhminFloating-Point Load
Instruction Behavior
FLH uses the I-type LOAD-FP encoding to load a 16-bit half-precision floating-point bit pattern from the effective address x[rs1] plus a signed 12-bit byte offset into floating-point register f[rd]. The transfer performs no FP rounding, format conversion, or NaN payload canonicalization; when written into a wider FLEN register, the half-precision value is stored using Zfh NaN-boxing rules. Atomicity of naturally aligned access follows the official Zfh rule, while misaligned access is constrained by the execution environment.
FLH Decode And Execute Animation
Shows the Zfh/Zfhmin-extension FP load flow: decode the I-type encoding, form the address from an integer base plus a 12-bit offset, and transfer a 16-bit FP bit pattern.
rd
offset
rs1
flh
,
,
Execution Context
fmt=H / width=16
base register is an integer x register
fflags unchanged
31..20
19..15
14..12
11..7
6..0
000000000010
imm[11:0]
01010
rs1
001
FLH
01010
rd
0000111
LOAD-FP
Execution Data Path
instruction
0x00251507
opcode
0000111 -> LOAD-FP
funct3
001 -> 16-bit load
offset
000000000010 -> 2
rd/rs1
fa0(f10) / a0(x10)
read
a0(x10) = 0x0000000000001000
address
0x0000000000001000 + (2) = 0x0000000000001002
write
fa0(f10) = 0x3E00
Current Step
Fetch: show the 32-bit I-type encoding
The word is split as a I-type instruction; FP memory access is not an OP-FP arithmetic encoding.
encoding: 0x00251507
syntax : flh fa0(f10), 2(a0(x10))
result : fa0(f10) = 0x3E00
Address And Bit-Pattern Transfer
base
0x0000000000001000
offset
2
address
0x0000000000001002
loaded bits
0x3E00
FLH transfers a 16-bit half-precision bit pattern and NaN-boxes the value written to rd under Zfh rules; the transfer preserves non-canonical NaN payloads.
This animation shows only Zfh/Zfhmin-extension FP load/store ISA-visible address calculation and bit-pattern transfer; it does not model caches, buses, trap handlers, FPU pipelines, or microarchitectural timing.
Quick Understanding & Search Notes
FLH is the Zfh/Zfhmin half-precision floating-point load. It forms the address from integer register rs1 plus a signed 12-bit byte offset, then loads a 16-bit half-precision bit pattern into FP register rd; this is not FP arithmetic and does not use rm rounding.
I-type LOAD-FP: imm[11:0], rs1, funct3=001, rd, opcode=0000111.
Effective address = x[rs1] + sign_extend(offset), with the offset measured in bytes.
FLH transfers a 16-bit half-precision bit pattern; writes into wider FLEN registers are NaN-boxed.
Common Usage Scenarios
Floating-Point Memory
Understand this scenario with real code like «flh f10, 0(x11) ; load half-precision from [x11]».
Data Load/Store
Understand this scenario with real code like «flh f10, 0(x11) ; load half-precision from [x11]».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register.
- rs1: integer base-address register.
- offset: signed 12-bit byte offset added to rs1 to form the effective address.
Semantic Check
- Confirm offset is a byte offset, not an element index.
- Check natural alignment and the execution environment's misaligned-access rules.
Pitfalls / Common Confusions
rs1 is an integer base register, not an FP register; rd is the FP destination register.
offset is a signed 12-bit byte offset in -2048..2047, not a half-precision element index.
FLH transfers a 16-bit bit pattern and performs no rounding or format conversion; writeback into wider FLEN registers uses NaN-boxing.
Only naturally aligned accesses have the specified atomicity guarantee; misaligned behavior depends on the execution environment.
FAQ
Does FLH convert half precision to single precision?
No. FLH is a bit-pattern load, not FCVT; it moves the half-precision encoding and stores it in wider FLEN registers using NaN-boxing.