Does FSH take the address from an FP register?
No. The address base comes from integer register rs1; FP register rs2 only supplies the data bit pattern to store.
FSH
RISC-V FSH Instruction Details
Instruction ManualS-typeStore a 16-bit half-precision bit pattern from an FP register to memory.
Instruction Syntax
fsh rs2, offset(rs1)
Operand Breakdown
rs2: FP f0–f31; rs1: integer x0–x31, with x0 supplying zero; these register files are distinct.
offset is a signed byte displacement in -2048..2047, with no rd, rm, or rs3; store low 16 bits, ignoring upper source bits without checking NaN-boxing.
ZfhZfhminFloating-Point Store
Instruction Behavior
FSH uses the S-type STORE-FP encoding to store the low 16 half-precision floating-point bits from floating-point register f[rs2] to the effective address x[rs1] plus a signed 12-bit byte offset. The store writes the format-width bits and performs no FP rounding, format conversion, or NaN payload canonicalization. Atomicity of naturally aligned access follows the official Zfh rule, while misaligned access is constrained by the execution environment.
FSH Decode And Execute Animation
Shows the Zfh/Zfhmin-extension FP store flow: decode the S-type encoding, form the address from an integer base plus a 12-bit offset, and transfer a 16-bit FP bit pattern.
rs2
offset
rs1
fsh
,
,
Execution Context
fmt=H / width=16
base register is an integer x register
fflags unchanged
31..25
24..20
19..15
14..12
11..7
6..0
0000000
imm[11:5]
01011
rs2
01010
rs1
001
FSH
00010
imm[4:0]
0100111
STORE-FP
Execution Data Path
instruction
0x00B51127
opcode
0100111 -> STORE-FP
funct3
001 -> 16-bit store
offset
000000000010 -> 2
rs2/rs1
fa1(f11) / a0(x10)
read
a0(x10) = 0x0000000000001000, fa1(f11) = 0x3E00
address
Awaiting Address
memory
Not stored yet; memory not updated
Current Step
Fetch: show the 32-bit S-type encoding
The word is split as a S-type instruction; FP memory access is not an OP-FP arithmetic encoding.
encoding: 0x00B51127
syntax : fsh fa1(f11), 2(a0(x10))
result : Not stored yet; memory not updated
Address And Bit-Pattern Transfer
base
0x0000000000001000
offset
2
address
Awaiting Address
alignment
2-byte aligned
stored bits
Not stored yet; memory not updated
FSH stores only the low 16 half-precision bits from rs2 and performs no rounding, format conversion, or NaN canonicalization. The current effective address is naturally aligned, so FSH has the official atomic-execution guarantee. This example is naturally aligned and cannot raise address-misaligned.
Assumes the extension and FS are enabled and the address is accessible. Shows the selected EEI branch without modeling protection or translation. The source input supplies the low bits; stores ignore higher bits without checking NaN-boxing. Steps are teaching views.
This animation shows only Zfh/Zfhmin-extension FP load/store ISA-visible address calculation and bit-pattern transfer; it does not model caches, buses, trap handlers, FPU pipelines, or microarchitectural timing.
Quick Understanding & Search Notes
FSH is the Zfh/Zfhmin half-precision floating-point store. It computes the address from an integer base and a 12-bit byte offset, then writes the 16-bit half-precision bit pattern from f[rs2] to memory; it performs no FP arithmetic and has no rm rounding field.
S-type STORE-FP: imm[11:5], rs2, rs1, funct3=001, imm[4:0], opcode=0100111.
Effective address = x[rs1] + sign_extend(offset), with the offset measured in bytes.
FSH stores the low 16 half-precision bits from the source FP register without canonicalizing NaN payloads.
Zfhmin 1.0 includes FSH, also supported by Zfh 1.0; both depend on F. Required extensions and FP state must be enabled.
The effective address wraps to XLEN; rs1=x0 reads zero. Successful stores leave source and base registers and fflags unchanged.
Common Usage Scenarios
Floating-Point Memory
Assume RV32/RV64 Zfhmin (or Zfh), enabled FP state, x10=0x1000, low f11 bits=0x3E00, writable memory and successful access: fsh f11, 2(x10) stores 0x3E00 unchanged to mem16[0x1002], leaving source, base and fflags unchanged without checking upper NaN-box bits.
Data Load/Store
Assume RV32/RV64 Zfhmin (or Zfh), enabled FP state, x10=0x1000, low f11 bits=0x3E00, writable memory and successful access: fsh f11, 2(x10) stores 0x3E00 unchanged to mem16[0x1002], leaving source, base and fflags unchanged without checking upper NaN-box bits.
Pre-Use Checklist
Syntax Check
- rs2: FP f0–f31; rs1: integer x0–x31, with x0 supplying zero; these register files are distinct.
- offset is a signed byte displacement in -2048..2047, with no rd, rm, or rs3; store low 16 bits, ignoring upper source bits without checking NaN-boxing.
Semantic Check
- Confirm offset is a byte offset, not an element index.
- Confirm the store writes the source floating-point encoding for that format without format conversion.
Pitfalls / Common Confusions
rs1 is an integer base register; rs2 is the FP source register.
offset is a signed 12-bit byte offset in -2048..2047.
FSH stores only the half-precision format-width bit pattern and performs no FP rounding or format conversion.
FSH does not write an FP register; load-time NaN-boxing is not a store-stage action.
Stores ignore every source bit above the low 16 bits without checking NaN-boxing; natural alignment is 2 bytes.
The EEI may complete a misaligned access or raise an exception; an exception does not guarantee unchanged memory.
FAQ
Does FSH change fflags?
No. FSH is a bit-pattern store and performs no FP arithmetic or rounding, so it does not set floating-point exception flags by ISA-visible semantics.