Does FSH take the address from an FP register?
No. The address base comes from integer register rs1; FP register rs2 only supplies the data bit pattern to store.
FSH
RISC-V FSH Instruction Details
Instruction ManualS-typeStore a 16-bit half-precision bit pattern from an FP register to memory.
Instruction Syntax
fsh rs2, offset(rs1)
Operand Breakdown
rs2: source floating-point register providing the encoding written to memory.
rs1: integer base-address register.
offset: signed 12-bit byte offset added to rs1 to form the effective address.
ZfhZfhminFloating-Point Store
Instruction Behavior
FSH uses the S-type STORE-FP encoding to store the low 16 half-precision floating-point bits from floating-point register f[rs2] to the effective address x[rs1] plus a signed 12-bit byte offset. The store writes the format-width bits and performs no FP rounding, format conversion, or NaN payload canonicalization. Atomicity of naturally aligned access follows the official Zfh rule, while misaligned access is constrained by the execution environment.
FSH Decode And Execute Animation
Shows the Zfh/Zfhmin-extension FP store flow: decode the S-type encoding, form the address from an integer base plus a 12-bit offset, and transfer a 16-bit FP bit pattern.
rs2
offset
rs1
fsh
,
,
Execution Context
fmt=H / width=16
base register is an integer x register
fflags unchanged
31..25
24..20
19..15
14..12
11..7
6..0
0000000
imm[11:5]
01011
rs2
01010
rs1
001
FSH
00010
imm[4:0]
0100111
STORE-FP
Execution Data Path
instruction
0x00B51127
opcode
0100111 -> STORE-FP
funct3
001 -> 16-bit store
offset
000000000010 -> 2
rs2/rs1
fa1(f11) / a0(x10)
read
a0(x10) = 0x0000000000001000, fa1(f11) = 0x3E00
address
0x0000000000001000 + (2) = 0x0000000000001002
memory
memory[0x0000000000001002] = 0x3E00
Current Step
Fetch: show the 32-bit S-type encoding
The word is split as a S-type instruction; FP memory access is not an OP-FP arithmetic encoding.
encoding: 0x00B51127
syntax : fsh fa1(f11), 2(a0(x10))
result : memory[0x0000000000001002] = 0x3E00
Address And Bit-Pattern Transfer
base
0x0000000000001000
offset
2
address
0x0000000000001002
stored bits
0x3E00
FSH stores only the low 16 half-precision bits from rs2 and performs no rounding, format conversion, or NaN canonicalization.
This animation shows only Zfh/Zfhmin-extension FP load/store ISA-visible address calculation and bit-pattern transfer; it does not model caches, buses, trap handlers, FPU pipelines, or microarchitectural timing.
Quick Understanding & Search Notes
FSH is the Zfh/Zfhmin half-precision floating-point store. It computes the address from an integer base and a 12-bit byte offset, then writes the 16-bit half-precision bit pattern from f[rs2] to memory; it is not an FP operation and has no rm rounding step.
S-type STORE-FP: imm[11:5], rs2, rs1, funct3=001, imm[4:0], opcode=0100111.
Effective address = x[rs1] + sign_extend(offset), with the offset measured in bytes.
FSH stores the low 16 half-precision bits from the source FP register without canonicalizing NaN payloads.
Common Usage Scenarios
Floating-Point Memory
Understand this scenario with real code like «fsh f10, 4(x11) ; store lower 16 bits of f10 to [x11+4]».
Data Load/Store
Understand this scenario with real code like «fsh f10, 4(x11) ; store lower 16 bits of f10 to [x11+4]».
Pre-Use Checklist
Syntax Check
- rs2: source floating-point register providing the encoding written to memory.
- rs1: integer base-address register.
- offset: signed 12-bit byte offset added to rs1 to form the effective address.
Semantic Check
- Confirm offset is a byte offset, not an element index.
- Confirm the store writes the source floating-point encoding for that format without format conversion.
Pitfalls / Common Confusions
rs1 is an integer base register; rs2 is the FP source register.
offset is a signed 12-bit byte offset in -2048..2047.
FSH stores only the half-precision format-width bit pattern and performs no FP rounding or format conversion.
FSH does not write an FP register; load-time NaN-boxing is not a store-stage action.
FAQ
Does FSH change fflags?
No. FSH is a bit-pattern store and performs no FP arithmetic or rounding, so it does not set floating-point exception flags by ISA-visible semantics.