RISC-V SRAIW Instruction Details
Instruction ManualI-typeShift 32-bit value in rs1 right arithmetically by immediate, sign-extend 32-bit result to 64 bits
Instruction Syntax
Instruction Encoding
SRAIW uses opcode 0011011 (0x1b), funct3 101, funct7 0100000. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Instruction Behavior
SRAIW (I-type, opcode=0011011, funct3=101, funct7=0100000) performs an arithmetic right shift on the lower 32 bits of rs1 (original sign bit is copied into the vacated upper bits) by the shift amount in imm[4:0]. The 32-bit result is sign-extended to 64 bits. imm[5] must be 0, otherwise the encoding is reserved.
Common Usage Scenarios
Understand this scenario with real code like «sraiw x10, x11, 2 # x10 = sign-extend((x11[31:0] >>> 2)[31:0])».
Understand this scenario with real code like «sraiw x10, x11, 2 # x10 = sign-extend((x11[31:0] >>> 2)[31:0])».
Pre-Use Checklist
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.