What happens with a shift amount of zero?
Keep rs1[31:0], then sign-extend bit 31 to 64 bits. For rs1=0x1234567880000000 and rd!=x0, the result is 0xffffffff80000000.
SRAIW
RISC-V SRAIW Instruction Details
Instruction ManualI-typeShift 32-bit value in rs1 right arithmetically by immediate, sign-extend 32-bit result to 64 bits
Instruction Syntax
sraiw rd, rs1, shamt
Operand Breakdown
rd: x0–x31; overlap reads old source values, and x0 writes are discarded.
shamt: 0–31; encodings with imm[5]=1 are reserved, not a signed 12-bit immediate.
RV64I-only; ignore upper 32 bits of rs1, copy original bit31 in an arithmetic right shift, then sign-extend the 32-bit result.
RV64IArithmetic32-bit Shift
Instruction Behavior
SRAIW is an I-type instruction with opcode=0011011, funct3=101, and fixed imm[11:5]=0100000. It arithmetically shifts the lower 32 bits of rs1 by imm[4:0], copying the original bit 31 into vacated upper bits, then sign-extends the 32-bit result to 64 bits. Encodings with imm[5] not equal to 0 are reserved.
SRAIW Decode And Execute Animation
RV64I; XLEN=64; 32-bit result → sign extension
sraiw rd, rs1, shamtExecution Context
Assume successful instruction fetch, no asynchronous interrupt or extra extension checks; one initial value per register.
This example fixes IALIGN=32 and a 32-bit instruction; PC must be 4-byte aligned.
32-bit encoding
0x4025D51Bfixed imm[11:5] [31..25]
0100000
shamt[4:0] [24..20]
00010
rs1 [19..15]
01011 → x11
funct3 [14..12]
101
rd [11..7]
01010 → x10
opcode [6..0]
0011011
x11=0xFFFFFFFFFFFFFFF0; shamt=2
Not computed
Fetch
Decode the current instruction fields and read sources before writeback; no result has been committed.
x10=0x0000000000000007; PC=0x0000000000002000
Current architectural state (before commit)
Current architectural state (before commit)
These are teaching steps for architectural effects, not processor pipeline stages or cycles.
Quick Understanding & Search Notes
SRAIW is RV64I-only: ignore the upper 32 bits of rs1, apply a 32-bit arithmetic right shift by shamt (0–31), then sign-extend to 64 bits.
opcode=0011011, funct3=101; imm[11:5]=0100000; encodings with imm[5]=1 are reserved.
A shift amount of zero still truncates to 32 bits and sign-extends; it does not copy the full 64-bit source.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «sraiw x10, x11, 1 # RV64I: x11=0x1234567880000000 -> x10=0xffffffffc0000000».
Pre-Use Checklist
Syntax Check
- rd, rs1 and optional rs2 select x0–x31 or ABI names; there is no rs3.
- shamt is 0–31; encodings with imm[5]=1 are reserved, not signed 12-bit operands.
Semantic Check
- Shift 32-bit value in rs1 right arithmetically by immediate, sign-extend 32-bit result to 64 bits
- Overlapping registers read sources before writeback; rd=x0 is a HINT, with only PC and applicable performance-counter advancement, and implementations may ignore it.
Pitfalls / Common Confusions
shamt is 0–31; encodings with imm[5]=1 are reserved, without guaranteeing a particular exception.
Arithmetic shift preserves sign, unlike SRLIW
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
These W-suffix forms belong to RV64I; RV32 has no corresponding forms.
rd=x0 is a custom HINT; it does not change architecturally visible state except PC and applicable performance counters, and an implementation may ignore it.
FAQ
Which bits supply the shift amount?
SRAIW uses imm[4:0], range 0–31. Encodings with imm[5]=1 are reserved; arbitrary out-of-range inputs cannot be masked into a legal instruction.