SRAW
RISC-V SRAW Instruction Details
Instruction ManualR-typeShift lower 32 bits of rs1 right arithmetically by rs2[4:0], sign-extend 32-bit result to 64 bits
Instruction Syntax
sraw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
RV64IArithmetic32-bit Shift
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
SRAW uses opcode 0111011 (0x3b), funct3 101, funct7 0100000. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0111011 (0x3b)
funct3: 101 (0x5)
funct7: 0100000 (0x20)
Instruction Behavior
SRAW (R-type, opcode=0111011, funct7=0100000, funct3=101) performs an arithmetic right shift on the lower 32 bits of rs1 (original sign bit copied into vacated upper bits) by the shift amount in rs2[4:0]. The 32-bit result is sign-extended to 64 bits.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «sraw x10, x11, x12 # x10 = sign-extend((x11[31:0] >>> x12[4:0])[31:0])».
Multiplication & Division
Understand this scenario with real code like «sraw x10, x11, x12 # x10 = sign-extend((x11[31:0] >>> x12[4:0])[31:0])».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Arithmetic shift preserves sign, ensuring correct signed semantics after extension
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
These W-suffix forms belong to RV64I or RV64 extension instructions; RV32 has no corresponding forms.