What happens with a shift amount of zero?
Keep rs1[31:0], then sign-extend bit 31 to 64 bits. For rs1=0x1234567880000000 and rd!=x0, the result is 0xffffffff80000000.
SRAW
RISC-V SRAW Instruction Details
Instruction ManualR-typeShift lower 32 bits of rs1 right arithmetically by rs2[4:0], sign-extend 32-bit result to 64 bits
Instruction Syntax
sraw rd, rs1, rs2
Operand Breakdown
rd: x0–x31; overlap reads old source values, and x0 writes are discarded.
rs2: only the low 5 bits supply the shift amount.
RV64I-only; ignore upper 32 bits of rs1, copy original bit31 in an arithmetic right shift, then sign-extend the 32-bit result.
RV64IArithmetic32-bit Shift
Instruction Behavior
SRAW (R-type, opcode=0111011, funct7=0100000, funct3=101) performs an arithmetic right shift on the lower 32 bits of rs1 (original sign bit copied into vacated upper bits) by the shift amount in rs2[4:0]. The 32-bit result is sign-extended to 64 bits.
SRAW Decode And Execute Animation
RV64I; XLEN=64; 32-bit result → sign extension
sraw rd, rs1, rs2Execution Context
Assume successful instruction fetch, no asynchronous interrupt or extra extension checks; one initial value per register.
This example fixes IALIGN=32 and a 32-bit instruction; PC must be 4-byte aligned.
32-bit encoding
0x40C5D53Bfunct7 [31..25]
0100000
rs2 [24..20]
01100 → x12
rs1 [19..15]
01011 → x11
funct3 [14..12]
101
rd [11..7]
01010 → x10
opcode [6..0]
0111011
x11=0xFFFFFFFFFFFFFFF0; x12=0x0000000000000002
Not computed
Fetch
Decode the current instruction fields and read sources before writeback; no result has been committed.
x10=0x0000000000000007; PC=0x0000000000002000
Current architectural state (before commit)
Current architectural state (before commit)
These are teaching steps for architectural effects, not processor pipeline stages or cycles.
Quick Understanding & Search Notes
SRAW is RV64I-only: ignore the upper 32 bits of rs1, apply a 32-bit arithmetic right shift by rs2[4:0], then sign-extend to 64 bits.
opcode=0111011, funct3=101; funct7=0100000.
A shift amount of zero still truncates to 32 bits and sign-extends; it does not copy the full 64-bit source.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «sraw x10, x11, x12 # RV64I: x11=0x1234567880000000, x12=33 -> x10=0xffffffffc0000000».
Pre-Use Checklist
Syntax Check
- rd, rs1 and optional rs2 select x0–x31 or ABI names; there is no rs3.
- The shift amount uses rs2[4:0].
Semantic Check
- Shift lower 32 bits of rs1 right arithmetically by rs2[4:0], sign-extend 32-bit result to 64 bits
- Overlapping registers read sources before writeback; rd=x0 is a HINT, with only PC and applicable performance-counter advancement, and implementations may ignore it.
Pitfalls / Common Confusions
Arithmetic shift preserves sign, ensuring correct signed semantics after extension
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
These W-suffix forms belong to RV64I; RV32 has no corresponding forms.
rd=x0 is a HINT designated for future standard use; it does not change architecturally visible state except PC and applicable performance counters, and an implementation may ignore it.
FAQ
Which bits supply the shift amount?
SRAW uses only rs2[4:0]; for example, rs2=33 shifts by 1.