Is it available on RV32?
No. SRLIW, SRLW, and SUBW are RV64I word-operation forms.
SRLIW
RISC-V SRLIW Instruction Details
Instruction ManualI-typeShift 32-bit value in rs1 right logically by immediate, sign-extend 32-bit result to 64 bits
Instruction Syntax
srliw rd, rs1, shamt
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV64IArithmetic32-bit Shift
Instruction Encoding
31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
SRLIW uses opcode 0011011 (0x1b), funct3 101, funct7 0000000. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Format: I-type
opcode: 0011011 (0x1b)
funct3: 101 (0x5)
funct7: 0000000 (0x00)
Instruction Behavior
SRLIW (I-type, opcode=0011011, funct3=101, funct7=0000000) performs a logical right shift on the lower 32 bits of rs1 (zeros are shifted into the upper bits) by the shift amount in imm[4:0]. The 32-bit result is sign-extended to 64 bits. imm[5] must be 0, otherwise the encoding is reserved.
Quick Understanding & Search Notes
SRLIW is an RV64I W-suffix integer instruction: it uses the low 32 bits of its inputs, produces a 32-bit result, then sign-extends bit 31 to 64 bits.
The W suffix is not a normal 64-bit operation; the written value is always a sign-extended 32-bit result.
SRLIW encodings with imm[5] set are reserved; the valid shift amount is 0..31.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «srliw x10, x11, 4 # x10 = sign-extend((x11[31:0] >> 4)[31:0])».
Multiplication & Division
Understand this scenario with real code like «srliw x10, x11, 4 # x10 = sign-extend((x11[31:0] >> 4)[31:0])».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Shift amounts >31 are reserved encodings
Result is sign-extended 32-bit after logical right shift
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
They exist in RV64/RV128-like environments, not RV32.
FAQ
Why can a logical shift still sign-extend?
The logical shift forms a 32-bit result first; the W-instruction rule then sign-extends bit 31 to 64 bits.