Is it available on RV32?
No. SRLIW, SRLW, and SUBW are RV64I word-operation forms.
SRLIW
RISC-V SRLIW Instruction Details
Instruction ManualI-typeShift 32-bit value in rs1 right logically by immediate, sign-extend 32-bit result to 64 bits
Instruction Syntax
srliw rd, rs1, shamt
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV64IArithmetic32-bit Shift
Instruction Behavior
SRLIW is an I-type instruction with opcode=0011011, funct3=101, and fixed imm[11:5]=0000000. It logically shifts the lower 32 bits of rs1 by imm[4:0], filling vacated upper bits with zero, then sign-extends the 32-bit result to 64 bits. Encodings with imm[5] not equal to 0 are reserved.
SRLIW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
shamt
srliw
,
,
Execution Context
t1(x6)
0x0000000000000014
31..25
24..20
19..15
14..12
11..7
6..0
0000000
fixed imm[11:5]
00010
shamt[4:0]
00110
rs1
101
funct3
00101
rd
0011011
opcode
Execution Data Path
instruction
0x0023529B
opcode
0011011 -> OP-IMM-32
funct3
101 -> SRLIW
imm[11:5]
imm[11:5]=0000000 fixed; shamt[4:0]=00010
rd / rs1
t0(x5) / t1(x6)
imm[11:5] + shamt[4:0]
imm[11:5]=0000000 fixed; shamt[4:0]=00010
32-bit logical shift
0x00000014 >> 2 -> low 32 bits 0x00000005 -> sext.w 0x0000000000000005
x5
t0(x5) = 0x0000000000000005
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x0023529B
syntax : srliw t0(x5), t1(x6), 2
result : t0(x5) = 0x0000000000000005
Architectural Result
t0(x5) = 0x0000000000000005
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SRLIW is an RV64I W-suffix integer instruction: it uses the low 32 bits of its inputs, produces a 32-bit result, then sign-extends bit 31 to 64 bits.
The W suffix is not a normal 64-bit operation; the written value is always a sign-extended 32-bit result.
SRLIW encodings with imm[5] set are reserved; the valid shift amount is 0..31.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «srliw x10, x11, 4 # x10 = sign-extend((x11[31:0] >> 4)[31:0])».
Pre-Use Checklist
Syntax Check
- Verify the immediate field is within the valid range.
- Confirm source register rs1 points to the correct operand.
Semantic Check
- Check if the immediate sign-extension matches expectations.
- Ensure the result register rd has a clear purpose.
Pitfalls / Common Confusions
Shift amounts >31 are reserved encodings
Result is sign-extended 32-bit after logical right shift
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
These W-suffix forms belong to RV64I; RV32 has no corresponding forms.
rd=x0 is a custom HINT; it does not change architecturally visible state except PC and applicable performance counters, and an implementation may ignore it.
FAQ
Why can a logical shift still sign-extend?
The logical shift forms a 32-bit result first; the W-instruction rule then sign-extends bit 31 to 64 bits.