Is it available on RV32?
No. SRLIW, SRLW, and SUBW are RV64I word-operation forms.
SRLW
RISC-V SRLW Instruction Details
Instruction ManualR-typeShift lower 32 bits of rs1 right logically by rs2[4:0], sign-extend 32-bit result to 64 bits
Instruction Syntax
srlw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
RV64IArithmetic32-bit Shift
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
SRLW uses opcode 0111011 (0x3b), funct3 101, funct7 0000000. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0111011 (0x3b)
funct3: 101 (0x5)
funct7: 0000000 (0x00)
Instruction Behavior
SRLW (R-type, opcode=0111011, funct7=0000000, funct3=101) performs a logical right shift on the lower 32 bits of rs1 (zeros shifted into upper bits) by the shift amount in rs2[4:0]. The 32-bit result is sign-extended to 64 bits.
Quick Understanding & Search Notes
SRLW is an RV64I W-suffix integer instruction: it uses the low 32 bits of its inputs, produces a 32-bit result, then sign-extends bit 31 to 64 bits.
The W suffix is not a normal 64-bit operation; the written value is always a sign-extended 32-bit result.
SRLW takes the shift amount from rs2[4:0]; upper bits do not contribute.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «srlw x10, x11, x12 # x10 = sign-extend((x11[31:0] >> x12[4:0])[31:0])».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Logical shift does not preserve sign bit, unlike SRAW
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
They exist in RV64/RV128-like environments, not RV32.
FAQ
Why can a logical shift still sign-extend?
The logical shift forms a 32-bit result first; the W-instruction rule then sign-extends bit 31 to 64 bits.