Is it available on RV32?
No. SRLIW, SRLW, and SUBW are RV64I word-operation forms.
SRLW
RISC-V SRLW Instruction Details
Instruction ManualR-typeShift lower 32 bits of rs1 right logically by rs2[4:0], sign-extend 32-bit result to 64 bits
Instruction Syntax
srlw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
RV64IArithmetic32-bit Shift
Instruction Behavior
SRLW (R-type, opcode=0111011, funct7=0000000, funct3=101) performs a logical right shift on the lower 32 bits of rs1 (zeros shifted into upper bits) by the shift amount in rs2[4:0]. The 32-bit result is sign-extended to 64 bits.
SRLW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
srlw
,
,
Execution Context
t1(x6)
0x0000000000000014
sp(x2)
0x0000000000000002
31..25
24..20
19..15
14..12
11..7
6..0
0000000
funct7
00010
rs2
00110
rs1
101
funct3
00101
rd
0111011
opcode
Execution Data Path
instruction
0x002352BB
opcode
0111011 -> OP-32
funct3
101 -> SRLW
funct7
0000000 -> base ALU op
rd / rs1 / rs2
t0(x5) / t1(x6) / sp(x2)
shamt
rs2[4:0]=00010 -> 2
32-bit logical shift
0x00000014 >> 2 -> low 32 bits 0x00000005 -> sext.w 0x0000000000000005
x5
t0(x5) = 0x0000000000000005
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x002352BB
syntax : srlw t0(x5), t1(x6), sp(x2)
result : t0(x5) = 0x0000000000000005
Architectural Result
t0(x5) = 0x0000000000000005
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SRLW is an RV64I W-suffix integer instruction: it uses the low 32 bits of its inputs, produces a 32-bit result, then sign-extends bit 31 to 64 bits.
The W suffix is not a normal 64-bit operation; the written value is always a sign-extended 32-bit result.
SRLW takes the shift amount from rs2[4:0]; upper bits do not contribute.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «srlw x10, x11, x12 # x10 = sign-extend((x11[31:0] >> x12[4:0])[31:0])».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
Logical shift does not preserve sign bit, unlike SRAW
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
SRLW is an RV64I instruction; RV32I has no W form of this instruction.
FAQ
Why can a logical shift still sign-extend?
The logical shift forms a 32-bit result first; the W-instruction rule then sign-extends bit 31 to 64 bits.