Is it available on RV32?
No. SRLIW, SRLW, and SUBW are RV64I word-operation forms.
SRLW
RISC-V SRLW Instruction Details
Instruction ManualR-typeShift lower 32 bits of rs1 right logically by rs2[4:0], sign-extend 32-bit result to 64 bits
Instruction Syntax
srlw rd, rs1, rs2
Operand Breakdown
rd: receives a 32-bit result sign-extended to 64 bits; x0 discards writes.
rs1: its low 32 bits are logically shifted right; rs2: only its low five bits supply the 0–31 shift amount.
RV64I-only, with no immediate operand; overlapping registers use source values before writeback.
RV64IArithmetic32-bit Shift
Instruction Behavior
SRLW (R-type, opcode=0111011, funct7=0000000, funct3=101) performs a logical right shift on the lower 32 bits of rs1 (zeros shifted into upper bits) by the shift amount in rs2[4:0]. The 32-bit result is sign-extended to 64 bits.
SRLW Decode And Execute Animation
RV64I; XLEN=64; 32-bit result → sign extension
srlw rd, rs1, rs2Execution Context
Assume successful instruction fetch, no asynchronous interrupt or extra extension checks; one initial value per register.
This example fixes IALIGN=32 and a 32-bit instruction; PC must be 4-byte aligned.
32-bit encoding
0x00C5D53Bfunct7 [31..25]
0000000
rs2 [24..20]
01100 → x12
rs1 [19..15]
01011 → x11
funct3 [14..12]
101
rd [11..7]
01010 → x10
opcode [6..0]
0111011
x11=0x0000000000000014; x12=0x0000000000000009
Not computed
Fetch
Decode the current instruction fields and read sources before writeback; no result has been committed.
x10=0x0000000000000007; PC=0x0000000000002000
Current architectural state (before commit)
Current architectural state (before commit)
These are teaching steps for architectural effects, not processor pipeline stages or cycles.
Quick Understanding & Search Notes
SRLW is RV64I-only: logically shift rs1[31:0] by rs2[4:0], then sign-extend bit 31 of the 32-bit result to 64 bits.
The W suffix is not a normal 64-bit operation; the written value is always a sign-extended 32-bit result.
SRLW takes the shift amount from rs2[4:0]; upper bits do not contribute.
rd, rs1, and rs2 use full five-bit integer-register fields; x0 reads as zero and discards writes. Encodings with rd=x0 are HINTs designated for future standard use.
Common Usage Scenarios
Bit Operations & Masks
RV64I, x11=0x1234567880000000 and x12=32: srlw x10, x11, x12 uses shift amount 0 and yields 0xffffffff80000000, ignoring the upper 32 bits of rs1.
Pre-Use Checklist
Syntax Check
- RV64I-only; rd, rs1 and rs2 are full five-bit GPR fields, with no rs3 or immediate.
Semantic Check
- Logically shift rs1[31:0] by rs2[4:0], then sign-extend bit 31 to 64 bits.
- Overlapping sources use pre-writeback values; rd=x0 is a HINT designated for future standard use, leaving registers and memory unchanged.
Pitfalls / Common Confusions
Logical shift does not preserve sign bit, unlike SRAW
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
SRLW is an RV64I instruction; RV32I has no W form of this instruction.
FAQ
Why can a logical shift still sign-extend?
The logical shift forms a 32-bit result first; the W-instruction rule then sign-extends bit 31 to 64 bits.