Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VCPOP.M
RISC-V VCPOP.M Instruction Details
Instruction ManualR-typeCount set bits in the active source mask and write the integer result to rd
Instruction Syntax
vcpop.m rd, vs2, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector Mask Operations
Instruction Behavior
VCPOP.M counts active set elements in the vs2 source mask and writes the count to integer register rd. With vm=0, only elements enabled by v0.t participate.
VCPOP.M Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VCPOP.M counts set bits in the active source mask and writes integer rd.
Instruction input
vcpop.m
OP-V encodingfunct6 | vm | vs2 | vs1=10000 | funct3 | rd | opcode
funct6
010000
vm
0
vs2
01000
vs1
10000
funct3
010
rd
01010
opcode
1010111
lane
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
v8
0
0
1
0
1
0
1
0
0
1
0
0
1
0
0
1
v0.t
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
scan
+0
off
+1
+0
+1
+0
off
+0
+0
+1
+0
off
+1
+0
+0
+1
x10
...
Current step
Show OP-V 32-bit encoding fields
vcpop.m uses OP-V encoding; the vs1 field is fixed to 10000, and vs1 is not a syntax operand.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active mask-bit scan within vl, and integer rd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VCPOP.M is an RVV mask-to-scalar instruction: it counts only active set source mask bits and writes integer rd.
The source operand vs2 is interpreted with mask-register layout; each element contributes one mask bit, not a SEW-width integer element.
Only body elements within the current vl are scanned; with vm=0, elements whose v0.t bit is 0 do not participate in first search or counting.
The official text reserves these instructions for an illegal-instruction exception when vstart is nonzero; the animation shows only the normal vstart=0 path.
The result is the number of active set bits and is written to scalar integer register rd, not a vector register.
Vector Execution Context
When reading VCPOP.M, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Loop Condition
Understand this scenario with real code like «vcpop.m rd, vs2».
Mask Density
Understand this scenario with real code like «vcpop.m rd, vs2».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The official mnemonic is vcpop.m; vpopc.m is only an older alias.
A nonzero vstart raises an illegal-instruction exception.
The source is mask register bits, not SEW-width data elements.
FAQ
Does VCPOP.M count positions where v0.t is 0?
No. With vm=0, elements whose v0.t bit is 0 are inactive and are not counted; with vm=1, all body elements within vl participate.
Does VCPOP.M write a vector register?
No. VCPOP.M writes the count to integer register rd.