How does VMSIF.M handle masking?
With vm=0, v0 selects active elements; with vm=1, all body elements participate. Inactive and tail elements follow the current policies.
VMSIF.M
RISC-V VMSIF.M Instruction Details
Instruction ManualR-typeGenerate a set-including-first destination mask from source mask vs2.
Instruction Syntax
vmsif.m vd, vs2, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector Mask Operations
Instruction Behavior
VMSIF.M is a RISC-V V mask-generation instruction. It scans source mask vs2 for the first set element and generates destination mask vd according to set-including-first semantics; source and destination use mask-register layout.
Quick Understanding & Search Notes
VMSIF.M is useful for turning the first matching element into a prefix, inclusive prefix, or single-bit mask.
vs2 is source mask data, not an ordinary integer vector.
With vm=0, v0 can restrict active elements participating in the scan; results and tails follow RVV mask rules.
vm=0 uses v0 as the execution mask and vm=1 is unmasked; inactive and tail elements follow the current vma/vta policy.
Common Usage Scenarios
Loop Termination
Understand this scenario with real code like «vmsif.m v1, v0».
Data-Dependent Exit
Understand this scenario with real code like «vmsif.m v1, v0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vmsbf.m/vmsif.m/vmsof.m differ at first set bit
Illegal instruction if vstart non-zero