How does VMSIF.M differ from VMSBF.M?
VMSIF.M includes the first position; VMSBF.M excludes it.
VMSIF.M
RISC-V VMSIF.M Instruction Details
Instruction ManualOPMVVSet mask positions up to and including the first active set bit
Instruction Syntax
vmsif.m vd, vs2[, v0.t]
Operand Breakdown
Syntax: vmsif.m vd, vs2[, v0.t]; omit v0.t for vm=1, include it for vm=0. vd is one mask register: bit i corresponds to element i, independent of SEW/LMUL.
32-bit OP-V: opcode=1010111, funct6=010100, funct3=010 (OPMVV), with vs1 fixed to 00011.
Search active source bits only. Active destination positions through the first active set source bit become 1; later active positions become 0. If none is found, every active result bit becomes 1. Nonzero vstart raises illegal-instruction, with trap vstart=0.
vd cannot overlap vs2; with vm=0, vd cannot be v0. vs2=v0 is legal; with vm=0, source and execution-mask bits must match.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW; vstart=0. Inactive follows vma; mask tails are always agnostic. vl=0 updates no destination bits, including tails. The animation fixes m1, VLEN=4096, vstart=0 and shows body elements only; steps are not processor cycles.
VVector Mask Operations
Instruction Behavior
VMSIF.M scans the vs2 source mask, finds the first active set element, writes 1 to active positions up to and including that first, and writes 0 to later active positions. If no active source bit is set, every active destination bit is written with 1.
VMSIF.M Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMSIF.M sets positions up to and including the first active set bit.
Instruction input
vmsif.m
Execution context
vstart0VMSIF.M requires vstart=0; a nonzero value raises an illegal-instruction exception and the trap reports vstart=0
The teaching model fixes vstart=0. VMSIF.M raises an illegal-instruction exception for nonzero vstart, so no ordinary nonzero-vstart execution path is shown.
Teaching context: SEW=8, LMUL=m1, VLEN=4096, VLMAX=512, vstart=0, valid vtype, and enabled VS; only body elements are shown. With no active source set bit, every active result bit is 1. x marks unspecified masked-off values; destination tails are always agnostic, while VL=0 updates nothing, including tails. With vm=0 and vs2=v0, source and execution-mask bits must match.
OP-V encodingfunct6 | vm | vs2 | vs1=00011 | funct3 | vd | opcode
funct6
010100
vm
0
vs2
01000
vs1
00011
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
v8
0
0
1
0
1
0
1
0
0
1
0
0
1
0
0
1
v0.t
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
scan
1
off
1
0
0
0
off
0
0
0
0
off
0
0
0
0
v4
...
...
...
...
...
...
...
...
...
...
...
...
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...
...
...
Current step
Show OP-V 32-bit encoding fields
vmsif.m uses OP-V encoding; the vs1 field is fixed to 00011, and vs1 is not a syntax operand.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active mask-bit scan within vl, and destination mask-bit writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMSIF.M generates an inclusive prefix mask: the first position itself is also set.
The source operand vs2 is interpreted with mask-register layout; each element contributes one mask bit, not a SEW-width integer element.
Only body elements within the current vl are scanned; with vm=0, elements whose v0.t bit is 0 do not participate in first search or result generation.
VMSIF.M raises an illegal-instruction exception when vstart is nonzero; such a trap always reports vstart=0, and the animation shows only the normal vstart=0 path.
Destination vd is a mask result; VMSIF.M writes 1 through the first active set bit and 0 after it.
If no active source element is 1, VMSIF.M writes 1 to every active destination position.
The destination mask register vd must not overlap source vs2; under masked execution, vd must also not overlap v0.
Masked-off destination elements are not deterministic zero; their value follows the current mask policy, and mask-result tail elements are tail-agnostic.
32-bit OP-V: opcode=1010111, funct6=010100, funct3=010 (OPMVV), with vs1 fixed to 00011. Omit v0.t for vm=1; include it for vm=0.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW. Bit i corresponds to element i, independent of SEW/LMUL. VL=0 updates no destination bits, including tails. With vm=0 and vs2=v0, source and execution-mask bits must match.
Vector Execution Context
Syntax: vmsif.m vd, vs2[, v0.t]; omit v0.t for vm=1, include it for vm=0. vd is one mask register: bit i corresponds to element i, independent of SEW/LMUL.
32-bit OP-V: opcode=1010111, funct6=010100, funct3=010 (OPMVV), with vs1 fixed to 00011.
Search active source bits only. Active destination positions through the first active set source bit become 1; later active positions become 0. If none is found, every active result bit becomes 1. Nonzero vstart raises illegal-instruction, with trap vstart=0.
vd cannot overlap vs2; with vm=0, vd cannot be v0. vs2=v0 is legal; with vm=0, source and execution-mask bits must match.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW; vstart=0. Inactive follows vma; mask tails are always agnostic. vl=0 updates no destination bits, including tails. The animation fixes m1, VLEN=4096, vstart=0 and shows body elements only; steps are not processor cycles.
Common Usage Scenarios
Loop Termination
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, and initialized sources; the example is unmasked. v0.mask[0..3]=[0,0,1,0] → v1.mask[0..3]=[1,1,1,0]. Only mask bits are written; tails are always agnostic without assumed zeroing.
Data-Dependent Exit
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, and initialized sources; the example is unmasked. v0.mask[0..3]=[0,0,1,0] → v1.mask[0..3]=[1,1,1,0]. Only mask bits are written; tails are always agnostic without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax: vmsif.m vd, vs2[, v0.t]; omit v0.t for vm=1, include it for vm=0. vd is one mask register: bit i corresponds to element i, independent of SEW/LMUL.
- 32-bit OP-V: opcode=1010111, funct6=010100, funct3=010 (OPMVV), with vs1 fixed to 00011.
Semantic Check
- Search active source bits only. Active destination positions through the first active set source bit become 1; later active positions become 0. If none is found, every active result bit becomes 1. Nonzero vstart raises illegal-instruction, with trap vstart=0.
- vd cannot overlap vs2; with vm=0, vd cannot be v0. vs2=v0 is legal; with vm=0, source and execution-mask bits must match.
- Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW; vstart=0. Inactive follows vma; mask tails are always agnostic. vl=0 updates no destination bits, including tails. The animation fixes m1, VLEN=4096, vstart=0 and shows body elements only; steps are not processor cycles.
Pitfalls / Common Confusions
vmsbf.m/vmsif.m/vmsof.m differ at the first position: before excludes first, including includes first, and only keeps first.
Destination vd must not overlap source vs2; under masked execution, destination vd must also not overlap v0.
A nonzero vstart raises an illegal-instruction exception.
Masked-off destination elements must not be treated as deterministic zero; their value follows the current mask policy, and tail elements are tail-agnostic.
FAQ
What if no active source bit is set, or VL=0?
With no active source set bit, each active destination bit becomes 1. With VL=0, every destination bit remains unchanged, including tails.