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VMSIF.M

RISC-V VMSIF.M Instruction Details

Instruction ManualR-type

Set mask positions up to and including the first active set bit

Instruction Syntax

vmsif.m vd, vs2, vm
Operand Breakdown
vd: mask destination register, with one Boolean result bit per element.
vs2/vs1 or scalar source: compared at the current SEW.
vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.
VVector Mask Operations
Related Search Terms
VMSIF.M instructionRISC-V vmsif.mvmsif.m syntaxset including firstRVV mask generationvmsif.m encoding

Instruction Behavior

VMSIF.M scans the vs2 source mask, finds the first active set element, and writes 1 to active positions up to and including that first; later positions are written as 0.

VMSIF.M Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VMSIF.M sets positions up to and including the first active set bit.

Instruction input
vmsif.m
OP-V encodingfunct6 | vm | vs2 | vs1=00011 | funct3 | vd | opcode
funct6
010100
vm
0
vs2
01000
vs1
00011
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
v8
0
0
1
0
1
0
1
0
0
1
0
0
1
0
0
1
v0.t
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
scan
1
off
1
0
0
0
off
0
0
0
0
off
0
0
0
0
v4
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
Current step

Show OP-V 32-bit encoding fields

vmsif.m uses OP-V encoding; the vs1 field is fixed to 00011, and vs1 is not a syntax operand.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active mask-bit scan within vl, and destination mask-bit writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VMSIF.M generates an inclusive prefix mask: the first position itself is also set.

The source operand vs2 is interpreted with mask-register layout; each element contributes one mask bit, not a SEW-width integer element.
Only body elements within the current vl are scanned; with vm=0, elements whose v0.t bit is 0 do not participate in first search or counting.
The official text reserves these instructions for an illegal-instruction exception when vstart is nonzero; the animation shows only the normal vstart=0 path.
Destination vd is a mask result; VMSIF.M writes 1 through the first active set bit and 0 after it.
The destination mask register vd must not overlap source vs2; under masked execution, vd must also not overlap v0.
Masked-off destination elements are not deterministic zero; their value follows the current mask policy, and mask-result tail elements are tail-agnostic.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VMSIF.M, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Loop Termination

Understand this scenario with real code like «vmsif.m v1, v0».

Data-Dependent Exit

Understand this scenario with real code like «vmsif.m v1, v0».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

vmsbf.m/vmsif.m/vmsof.m differ at the first position: before excludes first, including includes first, and only keeps first.
Destination vd must not overlap source vs2; under masked execution, destination vd must also not overlap v0.
A nonzero vstart raises an illegal-instruction exception.
Masked-off destination elements must not be treated as deterministic zero; their value follows the current mask policy, and tail elements are tail-agnostic.

FAQ

How does VMSIF.M differ from VMSBF.M?

VMSIF.M includes the first position; VMSBF.M excludes it.