Set only the first active set mask-bit position
VMSOF.M is a V-extension set-only-first mask instruction. Only the first active set-source position becomes 1; other active positions become 0, including when no active set source exists. Both source and destination use mask layout, rather than SEW-wide integer elements. vm=0 processes only body elements enabled by v0.t; vm=1 is unmasked. The result is a one-bit-per-element mask.
Starts from OP-V encoding fields, then shows how VMSOF.M sets only the first active set-bit position.
The teaching model fixes vstart=0. VMSOF.M raises an illegal-instruction exception for nonzero vstart, so no ordinary nonzero-vstart execution path is shown.
Teaching context: SEW=8, LMUL=m1, VLEN=4096, VLMAX=512, vstart=0, valid vtype, and enabled VS; only body elements are shown. Only the first active set-source position becomes 1; other active positions become 0, including when no active set source exists. x marks masked-off values governed by vma; mask tails are always agnostic, while VL=0 updates nothing, including tails. With vm=0 and vs2=v0, both bit strings must match. Steps are not processor cycles.
vmsof.m uses OP-V encoding; the vs1 field is fixed to 00010, and vs1 is not a syntax operand.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active mask-bit scan within vl, and destination mask-bit writeback. It does not model pipelines, caches, or timing.
Only the first active set-source position becomes 1; other active positions become 0, including when no active set source exists. Only active body bits are determined; the whole register is not guaranteed to be one-hot or all zero.
Syntax: vmsof.m vd, vs2[, v0.t]; omit v0.t for vm=1, include it for vm=0. vd is one mask register: bit i corresponds to element i, independent of SEW/LMUL.
32-bit OP-V: opcode=1010111, funct6=010100, funct3=010 (OPMVV). vs1 is fixed to 00010, selecting vmsof in VMUNARY0.
Only the first active set-source position becomes 1; other active positions become 0, including when no active set source exists. Both source and destination use mask layout, rather than SEW-wide integer elements.
vd cannot overlap vs2; with vm=0, vd cannot be v0. vs2=v0 is legal; with vm=0, source and execution-mask bits must match.
Require RV32/RV64 V 1.0, enabled VS, valid vtype and supported SEW. Nonzero vstart raises illegal-instruction; traps report vstart=0. Inactive follows vma; mask tails are always agnostic. vl=0 updates no destination bits, including tails.
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0 and initialized sources; the example is unmasked. v0.mask[0..3]=[0,0,1,1] → v1.mask[0..3]=[0,0,1,0]. Only active mask bits are determined; tails are always agnostic without assumed zeroing.
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0 and initialized sources; the example is unmasked. v0.mask[0..3]=[0,0,1,1] → v1.mask[0..3]=[0,0,1,0]. Only active mask bits are determined; tails are always agnostic without assumed zeroing.
Only the first active set-source position becomes 1; other active positions become 0, including when no active set source exists. Masked-off values follow vma; tails are always agnostic. VL=0 leaves everything unchanged.
vd cannot overlap vs2; with vm=0, vd cannot be v0. vs2=v0 is legal; with vm=0, source and execution-mask bits must match.