Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VMSOF.M
RISC-V VMSOF.M Instruction Details
Instruction ManualR-typeSet only the first active set mask-bit position
Instruction Syntax
vmsof.m vd, vs2, vm
Operand Breakdown
vd: mask destination register, with one Boolean result bit per element.
vs2/vs1 or scalar source: compared at the current SEW.
vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.
VVector Mask Operations
Instruction Behavior
VMSOF.M scans the vs2 source mask, finds the first active set element, and writes 1 only at that first position; other active positions are written as 0.
VMSOF.M Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMSOF.M sets only the first active set-bit position.
Instruction input
vmsof.m
OP-V encodingfunct6 | vm | vs2 | vs1=00010 | funct3 | vd | opcode
funct6
010100
vm
0
vs2
01000
vs1
00010
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
v8
0
0
1
0
1
0
1
0
0
1
0
0
1
0
0
1
v0.t
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
scan
0
off
1
0
0
0
off
0
0
0
0
off
0
0
0
0
v4
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
vmsof.m uses OP-V encoding; the vs1 field is fixed to 00010, and vs1 is not a syntax operand.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active mask-bit scan within vl, and destination mask-bit writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMSOF.M generates a one-hot mask: only the lowest-numbered active set-bit position is 1.
The source operand vs2 is interpreted with mask-register layout; each element contributes one mask bit, not a SEW-width integer element.
Only body elements within the current vl are scanned; with vm=0, elements whose v0.t bit is 0 do not participate in first search or counting.
The official text reserves these instructions for an illegal-instruction exception when vstart is nonzero; the animation shows only the normal vstart=0 path.
Destination vd is a mask result; VMSOF.M writes 1 only at the first active set bit and 0 at other active positions.
The destination mask register vd must not overlap source vs2; under masked execution, vd must also not overlap v0.
Masked-off destination elements are not deterministic zero; their value follows the current mask policy, and mask-result tail elements are tail-agnostic.
Vector Execution Context
When reading VMSOF.M, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Loop Termination
Understand this scenario with real code like «vmsof.m v1, v0».
Data-Dependent Exit
Understand this scenario with real code like «vmsof.m v1, v0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vmsbf.m/vmsif.m/vmsof.m differ at the first position: before excludes first, including includes first, and only keeps first.
Destination vd must not overlap source vs2; under masked execution, destination vd must also not overlap v0.
A nonzero vstart raises an illegal-instruction exception.
Masked-off destination elements must not be treated as deterministic zero; their value follows the current mask policy, and tail elements are tail-agnostic.
FAQ
What is the VMSOF.M result when no first bit is found?
When there is no active set bit, no one-hot 1 is produced and the animation shows all zeros. Inactive and tail positions remain governed by the current policies.