Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFIRST.M
RISC-V VFIRST.M Instruction Details
Instruction ManualR-typeFind the lowest-numbered active set mask bit and write integer rd
Instruction Syntax
vfirst.m rd, vs2, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector OperationsMask Operations
Instruction Behavior
VFIRST.M finds the lowest-numbered active set element in the vs2 source mask and writes that element index to integer register rd; if none is found, it writes -1.
VFIRST.M Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VFIRST.M finds the lowest-numbered active set bit, or writes -1 when none is found.
Instruction input
vfirst.m
OP-V encodingfunct6 | vm | vs2 | vs1=10001 | funct3 | rd | opcode
funct6
010000
vm
0
vs2
01000
vs1
10001
funct3
010
rd
01010
opcode
1010111
lane
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
v8
0
0
1
0
1
0
1
0
0
1
0
0
1
0
0
1
v0.t
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
scan
-
off
first
-
-
-
off
-
-
-
-
off
-
-
-
-
x10
...
Current step
Show OP-V 32-bit encoding fields
vfirst.m uses OP-V encoding; the vs1 field is fixed to 10001, and vs1 is not a syntax operand.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active mask-bit scan within vl, and integer rd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VFIRST.M is a mask-to-scalar search instruction: the result is the lowest-numbered active set-bit index, or -1 when none is found.
The source operand vs2 is interpreted with mask-register layout; each element contributes one mask bit, not a SEW-width integer element.
Only body elements within the current vl are scanned; with vm=0, elements whose v0.t bit is 0 do not participate in first search or counting.
The official text reserves these instructions for an illegal-instruction exception when vstart is nonzero; the animation shows only the normal vstart=0 path.
The result is written to scalar integer register rd; if no active element is 1, the result is -1.
Vector Execution Context
When reading VFIRST.M, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Conditional Loop
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmseq.vv v0, v8, v9 vfirst.m a0, v0».
Mask Traversal
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmseq.vv v0, v8, v9 vfirst.m a0, v0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Result in rd (x register), not vector. vs2 is mask source (not limited to v0). Returns -1 if none found.
FAQ
What does VFIRST.M return when no set bit is found?
It returns -1 in integer register rd.
Can VFIRST.M choose an inactive 1 as first?
No. With vm=0, positions whose v0.t bit is 0 do not participate, even if the vs2 bit is 1.