What does VFIRST.M return when no set bit is found?
It returns -1 in integer register rd.
VFIRST.M
RISC-V VFIRST.M Instruction Details
Instruction ManualV-typeFind the lowest-numbered active set mask bit and write integer rd
Instruction Syntax
vfirst.m rd, vs2, vm
Operand Breakdown
rd selects integer x0–x31 or an ABI name; vs2 is one mask register v0–v31, with one bit per element independent of SEW/LMUL.
The assembly vm operand is optional v0.t; omitting it means vm=1. With vm=0 only elements with v0[i]=1 participate.
Find the lowest active index i<vl with vs2[i]=1; no match, including vl=0, writes -1 to rd. rd=x0 discards writeback.
Require V, enabled vector state, and valid vector configuration. vstart must be 0; a nonzero value raises illegal instruction, and traps report vstart=0.
VVector OperationsMask Operations
Instruction Behavior
VFIRST.M finds the lowest-numbered active set element in the vs2 source mask and writes that element index to integer register rd; if none is found, it writes -1. It still writes -1 when vl=0, and raises an illegal-instruction exception when vstart is nonzero.
VFIRST.M Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VFIRST.M finds the lowest-numbered active set bit, or writes -1 when none is found.
Instruction input
vfirst.m
The teaching model fixes vstart=0. VFIRST.M raises an illegal-instruction exception for nonzero vstart; on the normal path it still writes -1 to rd when VL=0.
OP-V encodingfunct6 | vm | vs2 | vs1=10001 | funct3 | rd | opcode
funct6
010000
vm
0
vs2
01000
vs1
10001
funct3
010
rd
01010
opcode
1010111
lane
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
v8
0
0
1
0
1
0
1
0
0
1
0
0
1
0
0
1
v0.t
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
scan
-
off
first
-
-
-
off
-
-
-
-
off
-
-
-
-
x10
...
Current step
Show OP-V 32-bit encoding fields
vfirst.m uses OP-V encoding; the vs1 field is fixed to 10001, and vs1 is not a syntax operand.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active mask-bit scan within vl, and integer rd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VFIRST.M is a mask-to-scalar search instruction: the result is the lowest-numbered active set-bit index, or -1 when none is found.
The source operand vs2 is interpreted with mask-register layout; each element contributes one mask bit, not a SEW-width integer element.
Only body elements within the current vl are scanned; with vm=0, elements whose v0.t bit is 0 do not participate in the first-set search.
The official text requires vfirst.m to raise an illegal-instruction exception when vstart is nonzero; the animation shows only the normal vstart=0 path.
The result is written to scalar integer register rd; if no active element is 1, the result is -1.
Vector Execution Context
rd selects integer x0–x31 or an ABI name; vs2 is one mask register v0–v31, with one bit per element independent of SEW/LMUL.
The assembly vm operand is optional v0.t; omitting it means vm=1. With vm=0 only elements with v0[i]=1 participate.
Find the lowest active index i<vl with vs2[i]=1; no match, including vl=0, writes -1 to rd. rd=x0 discards writeback.
Require V, enabled vector state, and valid vector configuration. vstart must be 0; a nonzero value raises illegal instruction, and traps report vstart=0.
Common Usage Scenarios
First Set Mask Bit
Assume V/VS enabled, supported e32,m1, vstart=0, VLMAX≥4, a0=4 and v8 bits 0101 in lane order 0..3. The unmasked example gives a1=1; adding v0.t with v0 bits 1011 gives a1=3. No active set bit, or vl=0, gives -1.
Active Match Index
Assume V/VS enabled, supported e32,m1, vstart=0, VLMAX≥4, a0=4 and v8 bits 0101 in lane order 0..3. The unmasked example gives a1=1; adding v0.t with v0 bits 1011 gives a1=3. No active set bit, or vl=0, gives -1.
Pre-Use Checklist
Syntax Check
- rd selects integer x0–x31 or an ABI name; vs2 is one mask register v0–v31, with one bit per element independent of SEW/LMUL.
- The assembly vm operand is optional v0.t; omitting it means vm=1. With vm=0 only elements with v0[i]=1 participate.
Semantic Check
- Find the lowest active index i<vl with vs2[i]=1; no match, including vl=0, writes -1 to rd. rd=x0 discards writeback.
- Require V, enabled vector state, and valid vector configuration. vstart must be 0; a nonzero value raises illegal instruction, and traps report vstart=0.
Pitfalls / Common Confusions
The result is written to rd (an x register), not a vector register. vs2 is the mask source and is not limited to v0. It returns -1 when no match is found, including when vl=0.
A nonzero vstart raises an illegal-instruction exception; traps are reported with vstart=0.
FAQ
Can VFIRST.M choose an inactive 1 as first?
No. With vm=0, positions whose v0.t bit is 0 do not participate, even if the vs2 bit is 1.