Does VMSBF.M include the first position?
No. Active destination positions before the first active set source bit are 1; the first and later active positions are 0. With no active source set bit, all active destination bits are 1.
VMSBF.M
RISC-V VMSBF.M Instruction Details
Instruction ManualOPMVVWrite 1 to active mask positions before the first active set source bit, and 0 to other active positions.
Instruction Syntax
vmsbf.m vd, vs2[, v0.t]
Operand Breakdown
Syntax: vmsbf.m vd, vs2[, v0.t]; vs2 and vd are single mask registers with bit i corresponding to element i.
32-bit OP-V: opcode=1010111, funct6=010100, funct3=010 (OPMVV), with vs1 fixed to 00001. Omitting v0.t gives vm=1; including it gives vm=0.
Search active source bits only. Active destination positions before the first active set bit become 1, the first and later active positions become 0. If none is found, all active result bits become 1. vstart must be 0; nonzero raises illegal-instruction, with trap vstart=0.
vd cannot overlap vs2; with vm=0, vd also cannot be v0. vs2=v0 is legal, but source bits and execution-mask bits must match.
Require RV32/RV64 V 1.0, valid vtype, enabled VS, and supported SEW; vstart=0. Inactive elements follow vma; mask tails are always agnostic. VL=0 updates no destination, including tails. The animation shows only body elements in a fixed legal configuration; steps are not processor cycles.
VVector Mask Operations
Instruction Behavior
VMSBF.M scans active mask bits of vs2 within vl. It writes 1 to active destination positions before the first active set source bit, then 0 to that position and all later active positions. If no active source bit is set, all active destination bits become 1; inactive bits follow the mask policy.
VMSBF.M Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMSBF.M sets positions before the first active set bit.
Instruction input
vmsbf.m
vstart0VMSBF.M requires vstart=0; a nonzero value raises an illegal-instruction exception and the trap reports vstart=0
The teaching model fixes vstart=0. VMSBF.M raises an illegal-instruction exception for nonzero vstart, so no ordinary nonzero-vstart execution path is shown.
Teaching context: SEW=8, LMUL=m1, VLEN=4096, VLMAX=512, vstart=0, valid vtype, and enabled VS; only body elements are shown. With no active source set bit, every active result bit is 1. x marks unspecified masked-off values; destination tails are always agnostic, while VL=0 updates nothing, including tails. With vm=0 and vs2=v0, source and execution-mask bits must match.
OP-V encodingfunct6 | vm | vs2 | vs1=00001 | funct3 | vd | opcode
funct6
010100
vm
0
vs2
01000
vs1
00001
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
v8
0
0
1
0
1
0
1
0
0
1
0
0
1
0
0
1
v0.t
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
scan
1
off
0
0
0
0
off
0
0
0
0
off
0
0
0
0
v4
...
...
...
...
...
...
...
...
...
...
...
...
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...
Current step
Show OP-V 32-bit encoding fields
vmsbf.m uses OP-V encoding; the vs1 field is fixed to 00001, and vs1 is not a syntax operand.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active mask-bit scan within vl, and destination mask-bit writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMSBF.M generates the prefix mask before first: the first position itself is not set.
vs2 uses mask-register layout: one bit per element, independent of SEW.
Scan body elements within vl; with vm=0, v0.t=0 elements do not participate in the first-set-bit search.
Nonzero vstart raises an illegal-instruction exception; the animation fixes vstart=0.
vd is a mask: write 1 to active positions before the first active set source bit, and 0 at that position and later.
vd must not overlap vs2; with vm=0, vd must not overlap v0 either.
Masked-off values follow vma; mask tails are always agnostic. Neither is guaranteed zero.
With no active source set bit, all active result bits are 1. VL=0 updates nothing, including tails.
Vector Execution Context
Syntax: vmsbf.m vd, vs2[, v0.t]; vs2 and vd are single mask registers with bit i corresponding to element i.
32-bit OP-V: opcode=1010111, funct6=010100, funct3=010 (OPMVV), with vs1 fixed to 00001. Omitting v0.t gives vm=1; including it gives vm=0.
Search active source bits only. Active destination positions before the first active set bit become 1, the first and later active positions become 0. If none is found, all active result bits become 1. vstart must be 0; nonzero raises illegal-instruction, with trap vstart=0.
vd cannot overlap vs2; with vm=0, vd also cannot be v0. vs2=v0 is legal, but source bits and execution-mask bits must match.
Require RV32/RV64 V 1.0, valid vtype, enabled VS, and supported SEW; vstart=0. Inactive elements follow vma; mask tails are always agnostic. VL=0 updates no destination, including tails. The animation shows only body elements in a fixed legal configuration; steps are not processor cycles.
Common Usage Scenarios
Loop Termination
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, and initialized sources; The example is unmasked. v0.mask[0..3]=[0,0,1,0] → v1.mask[0..3]=[1,1,0,0]. Only mask bits are written; tails are always agnostic without assumed zeroing.
Data-Dependent Exit
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, and initialized sources; The example is unmasked. v0.mask[0..3]=[0,0,1,0] → v1.mask[0..3]=[1,1,0,0]. Only mask bits are written; tails are always agnostic without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax: vmsbf.m vd, vs2[, v0.t]; vs2 and vd are single mask registers with bit i corresponding to element i.
- 32-bit OP-V: opcode=1010111, funct6=010100, funct3=010 (OPMVV), with vs1 fixed to 00001. Omitting v0.t gives vm=1; including it gives vm=0.
Semantic Check
- Search active source bits only. Active destination positions before the first active set bit become 1, the first and later active positions become 0. If none is found, all active result bits become 1. vstart must be 0; nonzero raises illegal-instruction, with trap vstart=0.
- vd cannot overlap vs2; with vm=0, vd also cannot be v0. vs2=v0 is legal, but source bits and execution-mask bits must match.
- Require RV32/RV64 V 1.0, valid vtype, enabled VS, and supported SEW; vstart=0. Inactive elements follow vma; mask tails are always agnostic. VL=0 updates no destination, including tails. The animation shows only body elements in a fixed legal configuration; steps are not processor cycles.
Pitfalls / Common Confusions
vmsbf.m/vmsif.m/vmsof.m differ at the first position: before excludes first, including includes first, and only keeps first.
Destination vd must not overlap source vs2; under masked execution, destination vd must also not overlap v0.
A nonzero vstart raises an illegal-instruction exception.
Masked-off destination elements must not be treated as deterministic zero; their value follows the current mask policy, and tail elements are tail-agnostic.