Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VIOTA.M
RISC-V VIOTA.M Instruction Details
Instruction ManualR-typeCounts active set bits in the source mask before each element and writes the prefix count to integer vector vd.
Instruction Syntax
viota.m vd, vs2, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector PermutationMask Operations
Instruction Behavior
VIOTA.M is the RISC-V V extension mask-iota instruction. For each active body element i, it counts set bits in vs2 at lower indexes that participate in execution, then writes that prefix count to vd[i]. It is commonly used to turn a predicate mask into compact indexes for vcompress, scatter, or indexed-memory data paths.
VIOTA.M Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VIOTA.M writes the number of earlier active set bits into an integer vector.
Instruction input
viota.m
OP-V encodingfunct6 | vm | vs2 | vs1=10000 | funct3 | vd | opcode
funct6
010100
vm
0
vs2
01000
vs1
10000
funct3
010
vd
01100
opcode
1010111
lane
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
v8
0
0
1
0
1
0
1
0
0
1
0
0
1
0
0
1
v0.t
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
scan
0
off
0
1
1
2
off
2
2
2
3
off
3
4
4
4
v12
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
viota.m uses OP-V encoding; the vs1 field is fixed to 10000, and vs1 is not a syntax operand.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active mask-bit scan within vl, and destination integer-vector writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VIOTA.M turns a mask into integer indexes by asking each active lane how many selected 1 bits appear before it; the current lane itself is not counted.
Official syntax is `viota.m vd, vs2, vm`; OP-V VMUNARY0 encoding uses `funct6=010100`, `funct3=010`, `vs1=10000`, and vs2 supplies source mask bits.
For active body element i, the result is the number of active set bits in vs2 at indexes less than i; the current element itself is excluded from that lane count.
With vm=0, v0.t determines which elements participate; elements with v0.t=0 do not increment prefix counts for later lanes.
Destination vd receives SEW-wide integer results; if a count exceeds the SEW representation, only the low SEW bits are retained.
Vector Execution Context
When reading VIOTA.M, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Sparse Indexing
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmseq.vi v0, v8, 0 viota.m v12, v0, v0.t # active vd[i] = count of earlier active set bits».
Compress Helper
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmseq.vi v0, v8, 0 viota.m v12, v0, v0.t # active vd[i] = count of earlier active set bits».
Conditional Gather
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmseq.vi v0, v8, 0 viota.m v12, v0, v0.t # active vd[i] = count of earlier active set bits».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vs2 is the bit view of a mask register, not a normal SEW-wide integer vector; the output vd is the SEW-wide integer vector.
The count covers participating elements before the current lane: active set bits with indexes less than i, excluding the current lane itself.
With vm=0, lanes whose v0.t bit is 0 do not participate in the prefix count and do not write a deterministic result; do not treat a masked-off lane as contributing zero and still writing back.
If the prefix count is not representable in the current SEW, the low SEW bits are written; choose an SEW large enough for counts within vl in normal examples.
Overlap between destination vd and source vs2, or between vd and v0 during masked execution, is a reserved form; examples and animation avoid these combinations.
FAQ
Does VIOTA.M include the current lane bit in its result?
No. The result for lane i counts only active set bits at indexes less than i, so the first active lane can produce 0.
Is VIOTA.M output still a mask?
No. vs2 is a mask-bit input, but vd is an integer vector result; each active element receives a SEW-wide prefix count.
Do lanes disabled by v0.t affect later prefix counts?
No. With vm=0, only elements whose v0.t bit is 1 participate in iota counting and writeback; disabled lanes do not increment later counts.