Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VRGATHER.VV
RISC-V VRGATHER.VV Instruction Details
Instruction ManualR-typeGather vector elements from vs2 using per-lane indexes from vs1.
Instruction Syntax
vrgather.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector PermutationGather
Instruction Behavior
VRGATHER.VV uses each SEW-width element of vs1 as an element index, selects that element from vs2, and writes it to vd; an index greater than or equal to VLMAX produces zero.
VRGATHER.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VRGATHER uses the second source as element indexes, gathers from vs2 within VLMAX, and writes zero for out-of-range indexes.
Instruction input
vrgather.vv
OP-V encodingvrgather.vv
funct6
001100
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0002
0x0007
0x000c
0x0011
0x0016
0x001b
0x0020
0x0025
idx
idx
idx
idx
idx
idx
idx
idx
v12
0x0003
0x0000
0x0009
0x0005
0x0001
0x0007
0x0002
0x000c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vrgather.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, element-index/packing/select/move rearrangement integer indexed gather, boundary/selection rules, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
vrgather.vv treats each active lane's vs1 element as an element index and reads vs2[index]; indexes beyond VLMAX write zero.
OP-V encoding uses funct6=001100 and funct3=000 for vrgather.vv.
Indexes select source-vector elements and do not access memory.
vm controls whether body elements update; masked-off elements follow the current mask policy.
Encodings with destination/source register-group overlap between vd and vs2 or vs1 are reserved.
Vector Execution Context
When reading VRGATHER.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Table Lookup
Understand this scenario with real code like «vrgather.vv v8, v12, v4, v0.t».
Reorder
Understand this scenario with real code like «vrgather.vv v8, v12, v4, v0.t».
Compress/Decompress
Understand this scenario with real code like «vrgather.vv v8, v12, v4, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The index is a vs2 element number, not a memory address or byte offset.
An index >= VLMAX produces a zero result element without an exception.
vs1 index elements have the current SEW width; compare vrgatherei16.vv when 16-bit index elements are needed.
The vd destination register group must not overlap the vs2 or vs1 source vector register groups.
FAQ
Are vrgather.vv indexes byte offsets?
No. The index selects a vs2 element number; byte offsets belong to indexed load/store, not register gather.