Are vrgather.vv indexes byte offsets?
No. The index selects a vs2 element number; byte offsets belong to indexed load/store, not register gather.
VRGATHER.VV
RISC-V VRGATHER.VV Instruction Details
Instruction ManualOPIVV (OP-V)Gather vector elements from vs2 using per-lane indexes from vs1.
Instruction Syntax
vrgather.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
Syntax: vrgather.vv vd, vs2, vs1[, v0.t]; omit the mask for vm=1, include v0.t for vm=0. 32-bit OP-V: opcode=1010111, funct3=000 (OPIVV), funct6=001100.
Each unsigned SEW-width vs1 element is an element index. Sources may be read beyond vl but below VLMAX; indexes ≥VLMAX return zero. No memory is accessed.
Active body satisfies vstart≤i<vl with the mask enabled. Inactive/tail follow vma/vta: retain or agnostic, without a fixed value to rely on. vl=0 updates no destination elements.
vd must not overlap any source vector register group; such encodings are reserved. Masked vd cannot be v0; v0 cannot provide both the EEW=1 mask and SEW data. Group starts align to EMUL, EMUL≤8.
Require V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLMAX×SEW gives the current teaching configuration's VLEN. Steps are not processor cycles.
VVector PermutationGather
Instruction Behavior
VRGATHER.VV uses each SEW-width element of vs1 as an element index, selects that element from vs2, and writes it to vd; an index greater than or equal to VLMAX produces zero.
VRGATHER.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VRGATHER uses the second source as element indexes, gathers from vs2 within VLMAX, and writes zero for out-of-range indexes.
Instruction input
vrgather.vv
Require V 1.0, enabled vector state and valid supported vtype/SEW; fix LMUL=m1 and vstart=0. This teaching configuration has VLEN=VLMAX×SEW=256; changing SEW/VLMAX switches configurations. Sources may be read beyond vl but below VLMAX; indexes ≥VLMAX return zero. vd must not overlap any source. Indexes are unsigned. Masked vd cannot be v0; v0 cannot supply both mask and SEW data. Enter nonnegative element bit patterns. VL=0 leaves vd unchanged. Only body is shown; no definite inactive/tail values. Teaching stages are not processor cycles.
Execution Context
OP-V encodingvrgather.vv
funct6
001100
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0002
0x0007
0x000c
0x0011
0x0016
0x001b
0x0020
0x0025
idx
idx
idx
idx
idx
idx
idx
idx
v12
0x0003
0x0000
0x0009
0x0005
0x0001
0x0007
0x0002
0x000c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vrgather.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows OP-V field decode, active-element reads, indexed gather, mask control, and vd writeback. These are teaching stages; they do not model pipelines, caches, or timing.
Quick Understanding & Search Notes
vrgather.vv treats each active lane's vs1 element as an element index and reads vs2[index]; indexes at or above VLMAX write zero.
32-bit OP-V: opcode=1010111, funct3=000 (OPIVV), funct6=001100.
Indexes select source-vector elements and do not access memory.
vm controls whether body elements update; masked-off elements follow the current mask policy.
Encodings with destination/source register-group overlap between vd and vs2 or vs1 are reserved.
Indexes are unsigned and may read source elements beyond vl but below VLMAX. Inactive/tail follow vma/vta; vl=0 leaves vd unchanged.
Vector Execution Context
Syntax: vrgather.vv vd, vs2, vs1[, v0.t]; omit the mask for vm=1, include v0.t for vm=0. 32-bit OP-V: opcode=1010111, funct3=000 (OPIVV), funct6=001100.
Each unsigned SEW-width vs1 element is an element index. Sources may be read beyond vl but below VLMAX; indexes ≥VLMAX return zero. No memory is accessed.
Active body satisfies vstart≤i<vl with the mask enabled. Inactive/tail follow vma/vta: retain or agnostic, without a fixed value to rely on. vl=0 updates no destination elements.
vd must not overlap any source vector register group; such encodings are reserved. Masked vd cannot be v0; v0 cannot provide both the EEW=1 mask and SEW data. Group starts align to EMUL, EMUL≤8.
Require V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLMAX×SEW gives the current teaching configuration's VLEN. Steps are not processor cycles.
Common Usage Scenarios
Register table lookup
Assume enabled V/VS, valid m1, supported SEW, VLEN=128, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, VLMAX=16, v12=[10,20,30,40,...], v4=[3,0,16,1] → v8=[40,10,0,20]. Inactive/tail follow vma/vta; vl=0 leaves vd unchanged.
Vector element permutation
Assume enabled V/VS, valid m1, supported SEW, VLEN=128, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, VLMAX=16, v12=[10,20,30,40,...], v4=[3,0,16,1] → v8=[40,10,0,20]. Inactive/tail follow vma/vta; vl=0 leaves vd unchanged.
Pre-Use Checklist
Syntax Check
- Syntax: vrgather.vv vd, vs2, vs1[, v0.t]; omit the mask for vm=1, include v0.t for vm=0. 32-bit OP-V: opcode=1010111, funct3=000 (OPIVV), funct6=001100.
- Each unsigned SEW-width vs1 element is an element index. Sources may be read beyond vl but below VLMAX; indexes ≥VLMAX return zero. No memory is accessed.
Semantic Check
- Active body satisfies vstart≤i<vl with the mask enabled. Inactive/tail follow vma/vta: retain or agnostic, without a fixed value to rely on. vl=0 updates no destination elements.
- vd must not overlap any source vector register group; such encodings are reserved. Masked vd cannot be v0; v0 cannot provide both the EEW=1 mask and SEW data. Group starts align to EMUL, EMUL≤8.
- Require V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLMAX×SEW gives the current teaching configuration's VLEN. Steps are not processor cycles.
Pitfalls / Common Confusions
The index is a vs2 element number, not a memory address or byte offset.
An index >= VLMAX produces a zero result element without an exception.
vs1 index elements have the current SEW width; compare vrgatherei16.vv when 16-bit index elements are needed.
The vd destination register group must not overlap the vs2 or vs1 source vector register groups.