Does vrgather.vx truncate x[rs1] to SEW?
No. x[rs1] is used as an element index; the animation treats it as an XLEN-wide nonnegative index and writes zero when the index is >= VLMAX.
VRGATHER.VX
RISC-V VRGATHER.VX Instruction Details
Instruction ManualOPIVX (OP-V)Gather from vs2 using the scalar x[rs1] index for each active lane.
Instruction Syntax
vrgather.vx vd, vs2, rs1[, v0.t]
Operand Breakdown
Syntax: vrgather.vx vd, vs2, rs1[, v0.t]; omit the mask for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=100 (OPIVX), funct6=001100.
rs1 supplies an unsigned XLEN-wide index, not truncated to SEW; x0 supplies zero. Indexes select vs2 element numbers, including beyond vl but below VLMAX; indexes ≥VLMAX return zero without accessing memory.
Body is vstart≤i<vl; only mask-enabled body elements execute, with inactive/tail following vma/vta. Prestart is unchanged; vl=0 or vstart≥vl updates no destination elements.
vd cannot overlap any source vector register group; an ordinary masked vd cannot be v0. When v0 supplies EEW=1 mask/borrow bits it cannot also supply data; source groups cannot read a register with different EEWs. Group starts align to EMUL, EMUL≤8.
Require RV32/RV64 V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=VLMAX×SEW≥128. Only body is shown; steps are not processor cycles.
VVector PermutationGather
Instruction Behavior
VRGATHER.VX uses x[rs1] as the element index so active destination elements read the same indexed position from vs2; an index greater than or equal to VLMAX produces zero.
VRGATHER.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VRGATHER uses the second source as element indexes, gathers from vs2 within VLMAX, and writes zero for out-of-range indexes.
Instruction input
vrgather.vx
Require V 1.0, enabled vector state and valid supported vtype/SEW; fix LMUL=m1 and vstart=0. This teaching configuration has VLEN=VLMAX×SEW=256 (at least 128 bits). Sources may be read beyond vl but below VLMAX; indexes ≥VLMAX return zero. Indexes are unsigned; vd cannot overlap any source group. Scalar indexes use full XLEN; x0 supplies zero. When v0 supplies the EEW=1 mask/borrow bits it cannot also supply data. Enter nonnegative element bit patterns. VL=0 updates no destination bits. Only body is shown without definite inactive/tail values; teaching stages are not processor cycles.
Execution Context
OP-V encodingvrgather.vx
funct6
001100
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0002
0x0007
0x000c
0x0011
0x0016
0x001b
0x0020
0x0025
idx
idx
idx
idx
idx
idx
idx
idx
x11
0x0000000000000003
0x0000000000000003
0x0000000000000003
0x0000000000000003
0x0000000000000003
0x0000000000000003
0x0000000000000003
0x0000000000000003
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vrgather.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows OP-V field decode, indexed gather, execution masking, and vd writeback; teaching stages are not processor cycles.
Quick Understanding & Search Notes
vrgather.vx uses x[rs1] as one shared element index, so active lanes read vs2[x[rs1]]; an out-of-range index writes zero.
OP-V encoding uses funct6=001100 and funct3=100 for vrgather.vx.
x[rs1] is used as a nonnegative element index, not as a data element or byte address.
vm controls whether body elements update.
Encodings with destination/source register-group overlap between vd and vs2 are reserved.
Indexes are unsigned and may read source elements beyond vl but below VLMAX. Inactive/tail follow vma/vta; vl=0 leaves vd unchanged.
Vector Execution Context
Syntax: vrgather.vx vd, vs2, rs1[, v0.t]; omit the mask for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=100 (OPIVX), funct6=001100.
rs1 supplies an unsigned XLEN-wide index, not truncated to SEW; x0 supplies zero. Indexes select vs2 element numbers, including beyond vl but below VLMAX; indexes ≥VLMAX return zero without accessing memory.
Body is vstart≤i<vl; only mask-enabled body elements execute, with inactive/tail following vma/vta. Prestart is unchanged; vl=0 or vstart≥vl updates no destination elements.
vd cannot overlap any source vector register group; an ordinary masked vd cannot be v0. When v0 supplies EEW=1 mask/borrow bits it cannot also supply data; source groups cannot read a register with different EEWs. Group starts align to EMUL, EMUL≤8.
Require RV32/RV64 V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=VLMAX×SEW≥128. Only body is shown; steps are not processor cycles.
Common Usage Scenarios
Register table lookup
Assume enabled V/VS, valid m1, supported SEW, VLEN=128, vl=4, vstart=0 and initialized sources, v0.mask[0..3]=1111. SEW=8, VLMAX=16, x5=3, v12[3]=40 → v8=[40,40,40,40]. Inactive/tail follow vma/vta. vl=0 leaves vd unchanged.
Vector element permutation
Assume enabled V/VS, valid m1, supported SEW, VLEN=128, vl=4, vstart=0 and initialized sources, v0.mask[0..3]=1111. SEW=8, VLMAX=16, x5=3, v12[3]=40 → v8=[40,40,40,40]. Inactive/tail follow vma/vta. vl=0 leaves vd unchanged.
Pre-Use Checklist
Syntax Check
- Syntax: vrgather.vx vd, vs2, rs1[, v0.t]; omit the mask for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=100 (OPIVX), funct6=001100.
- rs1 supplies an unsigned XLEN-wide index, not truncated to SEW; x0 supplies zero. Indexes select vs2 element numbers, including beyond vl but below VLMAX; indexes ≥VLMAX return zero without accessing memory.
Semantic Check
- Body is vstart≤i<vl; only mask-enabled body elements execute, with inactive/tail following vma/vta. Prestart is unchanged; vl=0 or vstart≥vl updates no destination elements.
- vd cannot overlap any source vector register group; an ordinary masked vd cannot be v0. When v0 supplies EEW=1 mask/borrow bits it cannot also supply data; source groups cannot read a register with different EEWs. Group starts align to EMUL, EMUL≤8.
- Require RV32/RV64 V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=VLMAX×SEW≥128. Only body is shown; steps are not processor cycles.
Pitfalls / Common Confusions
x[rs1] is an element index and is not truncated to SEW.
In a legal configuration, an index >= VLMAX returns zero; this instruction does not access memory.
All active lanes use the same scalar index.
The vd destination register group must not overlap the vs2 source vector register group.