Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VRGATHER.VX
RISC-V VRGATHER.VX Instruction Details
Instruction ManualR-typeGather from vs2 using the scalar x[rs1] index for each active lane.
Instruction Syntax
vrgather.vx vd, vs2, rs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector PermutationGather
Instruction Behavior
VRGATHER.VX uses x[rs1] as the element index so active destination elements read the same indexed position from vs2; an index greater than or equal to VLMAX produces zero.
VRGATHER.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VRGATHER uses the second source as element indexes, gathers from vs2 within VLMAX, and writes zero for out-of-range indexes.
Instruction input
vrgather.vx
OP-V encodingvrgather.vx
funct6
001100
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0002
0x0007
0x000c
0x0011
0x0016
0x001b
0x0020
0x0025
idx
idx
idx
idx
idx
idx
idx
idx
x11
0x0000000000000003
0x0000000000000003
0x0000000000000003
0x0000000000000003
0x0000000000000003
0x0000000000000003
0x0000000000000003
0x0000000000000003
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vrgather.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, element-index/packing/select/move rearrangement integer indexed gather, boundary/selection rules, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
vrgather.vx uses x[rs1] as one shared element index, so active lanes read vs2[x[rs1]]; an out-of-range index writes zero.
OP-V encoding uses funct6=001100 and funct3=100 for vrgather.vx.
x[rs1] is used as a nonnegative element index, not as a data element or byte address.
vm controls whether body elements update.
Encodings with destination/source register-group overlap between vd and vs2 are reserved.
Vector Execution Context
When reading VRGATHER.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Table Lookup
Understand this scenario with real code like «vrgather.vx v8, v12, x5, v0.t».
Reorder
Understand this scenario with real code like «vrgather.vx v8, v12, x5, v0.t».
Compress/Decompress
Understand this scenario with real code like «vrgather.vx v8, v12, x5, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
x[rs1] is an element index and is not truncated to SEW.
An index >= VLMAX writes zero, with no memory access and no exception.
All active lanes use the same scalar index.
The vd destination register group must not overlap the vs2 source vector register group.
FAQ
Does vrgather.vx truncate x[rs1] to SEW?
No. x[rs1] is used as an element index; the animation treats it as an XLEN-wide nonnegative index and writes zero when the index is >= VLMAX.