Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VRGATHEREI16.VV
RISC-V VRGATHEREI16.VV Instruction Details
Instruction ManualR-typeGather vector elements from vs2 using 16-bit index elements.
Instruction Syntax
vrgatherei16.vv vd, vs2, vs1, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector PermutationGather
Instruction Behavior
VRGATHEREI16.VV uses EEW=16 index elements in vs1 to select elements from vs2 into vd; an index greater than or equal to VLMAX produces zero, and the index width is independent of data SEW.
VRGATHEREI16.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VRGATHEREI16 gathers vs2 data with 16-bit index elements whose width is independent of data SEW.
Instruction input
vrgatherei16.vv
OP-V encodingvrgatherei16.vv
funct6
001110
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0002
0x0007
0x000c
0x0011
0x0016
0x001b
0x0020
0x0025
idx16
idx16
idx16
idx16
idx16
idx16
idx16
idx16
v12
0x0003
0x0000
0x0009
0x0005
0x0001
0x0007
0x0002
0x000c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vrgatherei16.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, element-index/packing/select/move rearrangement integer 16-bit indexed gather, boundary/selection rules, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
vrgatherei16.vv is similar to vrgather.vv, but vs1 index elements are fixed at 16 bits; active lanes read vs2[index], and out-of-range indexes write zero.
OP-V encoding uses funct6=001110 and funct3=000 for vrgatherei16.vv.
The index EEW is 16 and may differ from data SEW.
vm controls whether body elements update.
Encodings with destination/source register-group overlap between vd and vs2 or vs1 are reserved.
Vector Execution Context
When reading VRGATHEREI16.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Large Table Lookup
Understand this scenario with real code like «vrgatherei16.vv v8, v12, v4, v0.t».
Sparse Data
Understand this scenario with real code like «vrgatherei16.vv v8, v12, v4, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vs1 index elements are fixed at 16 bits and are separate from data SEW.
The index selects a vs2 element number, not a memory address.
An index >= VLMAX writes zero.
The vd destination register group must not overlap the vs2 or vs1 source vector register groups.
FAQ
How does vrgatherei16.vv differ from vrgather.vv?
vrgatherei16.vv uses fixed 16-bit index elements; vrgather.vv uses index elements with the current SEW width. Both write zero for out-of-range indexes.