How does vrgatherei16.vv differ from vrgather.vv?
vrgatherei16.vv uses fixed 16-bit index elements; vrgather.vv uses index elements with the current SEW width. Both write zero for out-of-range indexes.
VRGATHEREI16.VV
RISC-V VRGATHEREI16.VV Instruction Details
Instruction ManualOPIVV (OP-V)Gather vector elements from vs2 using 16-bit index elements.
Instruction Syntax
vrgatherei16.vv vd, vs2, vs1[, v0.t]
Operand Breakdown
Syntax: vrgatherei16.vv vd, vs2, vs1[, v0.t]; omit the mask for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=000 (OPIVV), funct6=001110.
vs1 supplies unsigned EEW=16 indexes with EMUL=(16/SEW)×LMUL; vs2 data uses SEW/LMUL. Indexes select vs2 element numbers, including beyond vl but below VLMAX; indexes ≥VLMAX return zero without accessing memory.
Body is vstart≤i<vl; only mask-enabled body elements execute, with inactive/tail following vma/vta. Prestart is unchanged; vl=0 or vstart≥vl updates no destination elements.
vd cannot overlap any source vector register group; an ordinary masked vd cannot be v0. When v0 supplies EEW=1 mask/borrow bits it cannot also supply data; source groups cannot read a register with different EEWs. Group starts align to EMUL, EMUL≤8.
Require RV32/RV64 V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=VLMAX×SEW≥128. Only body is shown; steps are not processor cycles.
VVector PermutationGather
Instruction Behavior
VRGATHEREI16.VV uses EEW=16 index elements in vs1 to select elements from vs2 into vd; an index greater than or equal to VLMAX produces zero, and the index width is independent of data SEW.
VRGATHEREI16.VV Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VRGATHEREI16 gathers vs2 data with 16-bit index elements whose width is independent of data SEW.
Instruction input
vrgatherei16.vv
Require V 1.0, enabled vector state and valid supported vtype/SEW; fix LMUL=m1 and vstart=0. This teaching configuration has VLEN=VLMAX×SEW=256 (at least 128 bits). Sources may be read beyond vl but below VLMAX; indexes ≥VLMAX return zero. Indexes are unsigned; vd cannot overlap any source group. Index EEW=16, EMUL=1; EMUL=2 groups start at even registers and different-EEW source groups cannot overlap. When v0 supplies the EEW=1 mask/borrow bits it cannot also supply data. Enter nonnegative element bit patterns. VL=0 updates no destination bits. Only body is shown without definite inactive/tail values; teaching stages are not processor cycles.
Execution Context
OP-V encodingvrgatherei16.vv
funct6
001110
vm
0
vs2
01000
vs1
01100
funct3
000
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0002
0x0007
0x000c
0x0011
0x0016
0x001b
0x0020
0x0025
idx16
idx16
idx16
idx16
idx16
idx16
idx16
idx16
v12
0x0003
0x0000
0x0009
0x0005
0x0001
0x0007
0x0002
0x000c
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vrgatherei16.vv uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows OP-V field decode, 16-bit indexed gather, execution masking, and vd writeback; teaching stages are not processor cycles.
Quick Understanding & Search Notes
vrgatherei16.vv is similar to vrgather.vv, but vs1 index elements are fixed at 16 bits; active lanes read vs2[index], and out-of-range indexes write zero.
OP-V encoding uses funct6=001110 and funct3=000 for vrgatherei16.vv.
The index EEW is 16 and may differ from data SEW.
vm controls whether body elements update.
Encodings with destination/source register-group overlap between vd and vs2 or vs1 are reserved.
Indexes are unsigned and may read source elements beyond vl but below VLMAX. Inactive/tail follow vma/vta; vl=0 leaves vd unchanged.
The index group has EMUL=(16/SEW)×LMUL; group starts align to EMUL, and the same source register cannot be read with different EEWs.
Vector Execution Context
Syntax: vrgatherei16.vv vd, vs2, vs1[, v0.t]; omit the mask for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=000 (OPIVV), funct6=001110.
vs1 supplies unsigned EEW=16 indexes with EMUL=(16/SEW)×LMUL; vs2 data uses SEW/LMUL. Indexes select vs2 element numbers, including beyond vl but below VLMAX; indexes ≥VLMAX return zero without accessing memory.
Body is vstart≤i<vl; only mask-enabled body elements execute, with inactive/tail following vma/vta. Prestart is unchanged; vl=0 or vstart≥vl updates no destination elements.
vd cannot overlap any source vector register group; an ordinary masked vd cannot be v0. When v0 supplies EEW=1 mask/borrow bits it cannot also supply data; source groups cannot read a register with different EEWs. Group starts align to EMUL, EMUL≤8.
Require RV32/RV64 V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=VLMAX×SEW≥128. Only body is shown; steps are not processor cycles.
Common Usage Scenarios
Register table lookup
Assume enabled V/VS, valid m1, supported SEW, VLEN=128, vl=4, vstart=0 and initialized sources, v0.mask[0..3]=1111. SEW=8, VLMAX=16, v12=[10,20,30,40,...], v4(EEW=16)=[3,0,16,1] → v8=[40,10,0,20]. Inactive/tail follow vma/vta. vl=0 leaves vd unchanged.
Vector element permutation
Assume enabled V/VS, valid m1, supported SEW, VLEN=128, vl=4, vstart=0 and initialized sources, v0.mask[0..3]=1111. SEW=8, VLMAX=16, v12=[10,20,30,40,...], v4(EEW=16)=[3,0,16,1] → v8=[40,10,0,20]. Inactive/tail follow vma/vta. vl=0 leaves vd unchanged.
Pre-Use Checklist
Syntax Check
- Syntax: vrgatherei16.vv vd, vs2, vs1[, v0.t]; omit the mask for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=000 (OPIVV), funct6=001110.
- vs1 supplies unsigned EEW=16 indexes with EMUL=(16/SEW)×LMUL; vs2 data uses SEW/LMUL. Indexes select vs2 element numbers, including beyond vl but below VLMAX; indexes ≥VLMAX return zero without accessing memory.
Semantic Check
- Body is vstart≤i<vl; only mask-enabled body elements execute, with inactive/tail following vma/vta. Prestart is unchanged; vl=0 or vstart≥vl updates no destination elements.
- vd cannot overlap any source vector register group; an ordinary masked vd cannot be v0. When v0 supplies EEW=1 mask/borrow bits it cannot also supply data; source groups cannot read a register with different EEWs. Group starts align to EMUL, EMUL≤8.
- Require RV32/RV64 V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=VLMAX×SEW≥128. Only body is shown; steps are not processor cycles.
Pitfalls / Common Confusions
vs1 index elements are fixed at 16 bits and are separate from data SEW.
The index selects a vs2 element number, not a memory address.
An index >= VLMAX writes zero.
The vd destination register group must not overlap the vs2 or vs1 source vector register groups.