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VRGATHEREI16.VV

RISC-V VRGATHEREI16.VV Instruction Details

Instruction ManualR-type

Gather source-vector elements using 16-bit index elements.

Instruction Syntax

vrgatherei16.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector PermutationGather

Instruction Behavior

VRGATHEREI16.VV uses indices from vs1 to select elements from vs2 into vd; an index outside VLMAX produces a zero result element.

Quick Understanding & Search Notes

VRGATHEREI16.VV handles index-based rearrangement of vector elements, with source data coming from vs2.

The index selects an element of vs2; it is not a memory address.
An index outside VLMAX writes zero to the destination element.
VRGATHEREI16.VV uses fixed 16-bit index elements, allowing smaller index widths with larger data SEW.

Common Usage Scenarios

Large Table Lookup

Understand this scenario with real code like «vrgatherei16.vv v8, v12, v4, v0.t».

Sparse Data

Understand this scenario with real code like «vrgatherei16.vv v8, v12, v4, v0.t».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Index EEW fixed 16-bit independent of data SEW
OOB returns 0

FAQ

Are VRGATHEREI16.VV indices byte offsets?

No. VRGATHER indices select source-vector elements; byte offsets belong to indexed load/store instructions.