VRGATHER.VI

RISC-V VRGATHER.VI Instruction Details

Instruction ManualOPIVI (OP-V)

Gather the same indexed element from vs2 using a 5-bit immediate index.

Instruction Syntax

vrgather.vi vd, vs2, uimm[, v0.t]

Operand Breakdown

Syntax: vrgather.vi vd, vs2, uimm[, v0.t]; omit the mask for vm=1, include v0.t for vm=0. 32-bit OP-V: opcode=1010111, funct3=011 (OPIVI), funct6=001100.

The 5-bit zero-extended uimm (0..31) is an element index. Sources may be read beyond vl but below VLMAX; indexes ≥VLMAX return zero. No memory is accessed.

Active body satisfies vstart≤i<vl with the mask enabled. Inactive/tail follow vma/vta: retain or agnostic, without a fixed value to rely on. vl=0 updates no destination elements.

vd must not overlap any source vector register group; such encodings are reserved. Masked vd cannot be v0; v0 cannot provide both the EEW=1 mask and SEW data. Group starts align to EMUL, EMUL≤8.

Require V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLMAX×SEW gives the current teaching configuration's VLEN. Steps are not processor cycles.

VVector PermutationGather

Related Search Terms

vrgather.vi instruction RISC-V vrgather.vi vrgather.vi encoding RVV immediate gather immediate indexed gather uimm index

Instruction Behavior

VRGATHER.VI uses a 5-bit zero-extended immediate as the element index so active destination elements read the same indexed position from vs2; an index greater than or equal to VLMAX produces zero.

VRGATHER.VI Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VRGATHER uses the second source as element indexes, gathers from vs2 within VLMAX, and writes zero for out-of-range indexes.

Instruction input

vrgather.vi

vdUse v1-v31; v0 is the execution maskvs2Use v1-v31; v0 supplies the EEW=1 execution maskuimmUse 0..31vmexecution mask control

Require V 1.0, enabled vector state and valid supported vtype/SEW; fix LMUL=m1 and vstart=0. This teaching configuration has VLEN=VLMAX×SEW=256; changing SEW/VLMAX switches configurations. Sources may be read beyond vl but below VLMAX; indexes ≥VLMAX return zero. vd must not overlap any source. Indexes are unsigned. Masked vd cannot be v0; v0 cannot supply both mask and SEW data. Enter nonnegative element bit patterns. VL=0 leaves vd unchanged. Only body is shown; no definite inactive/tail values. Teaching stages are not processor cycles.

Execution Context

VLVLMAXSEWvs2 elementsNeed VLMAX=16 source elements; only vl=8 destination body lanes are shown

immediate value

3 -> index 3

5-bit unsigned uimm is zero-extended as the element index, not truncated by SEW

v0 mask bitscontinuous 0/1 bit string

OP-V encodingvrgather.vi

funct6

001100

vs2

01000

uimm

00011

funct3

011

00100

opcode

1010111

lane

0x0002

0x0007

0x000c

0x0011

0x0016

0x001b

0x0020

0x0025

idx

imm

0x0003

v0.t

...

Current step

Show OP-V 32-bit encoding fields

vrgather.vi uses OP-V encoding. The animation places fixed fields, register fields, vm, and the uimm field in one encoding strip.

This animation shows OP-V field decode, active-element reads, indexed gather, mask control, and vd writeback. These are teaching stages; they do not model pipelines, caches, or timing.

Quick Understanding & Search Notes

vrgather.vi uses the 5-bit zero-extended uimm as one shared element index, so active lanes read vs2[uimm]; an out-of-range index writes zero.

32-bit OP-V: opcode=1010111, funct3=011 (OPIVI), funct6=001100.

uimm is an element number, not a byte offset.

vm controls whether body elements update.

Encodings with destination/source register-group overlap between vd and vs2 are reserved.

Indexes are unsigned and may read source elements beyond vl but below VLMAX. Inactive/tail follow vma/vta; vl=0 leaves vd unchanged.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture

Vector Execution Context

Syntax: vrgather.vi vd, vs2, uimm[, v0.t]; omit the mask for vm=1, include v0.t for vm=0. 32-bit OP-V: opcode=1010111, funct3=011 (OPIVI), funct6=001100.

The 5-bit zero-extended uimm (0..31) is an element index. Sources may be read beyond vl but below VLMAX; indexes ≥VLMAX return zero. No memory is accessed.

Active body satisfies vstart≤i<vl with the mask enabled. Inactive/tail follow vma/vta: retain or agnostic, without a fixed value to rely on. vl=0 updates no destination elements.

vd must not overlap any source vector register group; such encodings are reserved. Masked vd cannot be v0; v0 cannot provide both the EEW=1 mask and SEW data. Group starts align to EMUL, EMUL≤8.

Require V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLMAX×SEW gives the current teaching configuration's VLEN. Steps are not processor cycles.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Assume enabled V/VS, valid m1, supported SEW, VLEN=128, vl=4, vstart=0, v0.mask[0..3]=1111 and initialized sources. SEW=8, VLMAX=16, v12[3]=40, uimm=3 → v8=[40,40,40,40]. Inactive/tail follow vma/vta; vl=0 leaves vd unchanged.

Vector element permutation

Pre-Use Checklist

Syntax Check

Syntax: vrgather.vi vd, vs2, uimm[, v0.t]; omit the mask for vm=1, include v0.t for vm=0. 32-bit OP-V: opcode=1010111, funct3=011 (OPIVI), funct6=001100.
The 5-bit zero-extended uimm (0..31) is an element index. Sources may be read beyond vl but below VLMAX; indexes ≥VLMAX return zero. No memory is accessed.

Semantic Check

Active body satisfies vstart≤i<vl with the mask enabled. Inactive/tail follow vma/vta: retain or agnostic, without a fixed value to rely on. vl=0 updates no destination elements.
vd must not overlap any source vector register group; such encodings are reserved. Masked vd cannot be v0; v0 cannot provide both the EEW=1 mask and SEW data. Group starts align to EMUL, EMUL≤8.
Require V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLMAX×SEW gives the current teaching configuration's VLEN. Steps are not processor cycles.

Pitfalls / Common Confusions

The immediate field is a 0..31 element index, not a signed immediate.

An index >= VLMAX produces zero.

All active lanes use the same immediate index.

The vd destination register group must not overlap the vs2 source vector register group.

FAQ

What is the immediate range for vrgather.vi?

It uses a 5-bit zero-extended immediate field, so the animation validates 0..31; if that index is greater than or equal to current VLMAX, the result element is zero.