Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VCOMPRESS.VM
RISC-V VCOMPRESS.VM Instruction Details
Instruction ManualR-typePack vs2 elements selected by the vs1 mask into contiguous positions starting at vd[0].
Instruction Syntax
vcompress.vm vd, vs2, vs1
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector PermutationPermutation
Instruction Behavior
VCOMPRESS.VM uses the explicit vs1 mask to select elements from vs2 and writes the selected elements contiguously from vd[0] in original order; it is encoded as an unmasked instruction, and destination elements after the packed result are tail elements.
VCOMPRESS.VM Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VCOMPRESS uses the explicit vs1 selection mask to pack selected vs2 elements in order starting at vd[0].
Instruction input
vcompress.vm
vm
1
fixed unmasked encoding, not a syntax operandimmediate value
0 -> 0x0000
5-bit signed imm is sign-extended to SEWOP-V encodingvcompress.vm
funct6
010111
vm
1
vs2
01000
vs1
00000
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0002
0x0007
0x000c
0x0011
0x0016
0x001b
0x0020
0x0025
pack
pack
pack
pack
pack
pack
pack
pack
vs1
1
0
1
1
1
0
1
1
v4
...
...
...
...
...
...
tail
tail
Current step
Show OP-V 32-bit encoding fields
vcompress.vm uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, element-index/packing/select/move rearrangement integer mask compress, boundary/selection rules, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
vcompress.vm performs stable compaction of source lanes with vs1=1 within vl: the first selected element writes vd[0], the second writes vd[1], and so on.
OP-V encoding uses funct6=010111, funct3=010, and vm=1.
vs1 is the selection-mask operand; this instruction has no separate execution mask.
Destination elements after the packed writes are tail elements governed by vtype.vta.
Encodings where vd overlaps vs2 or vs1 are reserved.
The official specification requires vcompress.vm to raise an illegal-instruction exception when vstart is nonzero.
Vector Execution Context
When reading VCOMPRESS.VM, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Sparse Compression
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmsgt.vi v0, v8, 10 vcompress.vm v12, v8, v0».
Stream Compaction
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmsgt.vi v0, v8, 10 vcompress.vm v12, v8, v0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vs1 is the explicit selection mask, not an extra v0.t execution mask.
The number of writes equals the count of set vs1 bits within vl.
Destination elements after the packed result are tail elements; do not assume old values are preserved.
The vd destination register group must not overlap the vs2 source vector register group or the vs1 source mask register.
If vstart is nonzero, vcompress.vm raises an illegal-instruction exception and reports vstart=0.
FAQ
Does vcompress.vm write zero for unselected elements?
No. Unselected source elements are not packed into the contiguous result; destination elements after the packed result are tail elements governed by vtype.vta.