Does vcompress.vm write zero for unselected elements?
No. Unselected source elements are not packed into the contiguous result; destination elements after the packed result are tail elements governed by vtype.vta.
VCOMPRESS.VM
RISC-V VCOMPRESS.VM Instruction Details
Instruction ManualV-typePack vs2 elements selected by the vs1 mask into contiguous positions starting at vd[0].
Instruction Syntax
vcompress.vm vd, vs2, vs1
Operand Breakdown
vs2 supplies SEW-wide source elements; vs1 is the explicit EEW=1 selection mask. Select from the first vl elements and pack in source order starting at vd[0].
vm is fixed to 1; vm=0 is reserved, and the syntax has no additional v0.t execution mask.
vd cannot overlap vs2 or vs1; vs2 and vs1 cannot read one register at different EEWs. Destination elements after the packed result are tails governed by vta.
Require V, supported vtype, and vstart=0; nonzero vstart raises illegal-instruction, with traps reporting vstart=0.
VVector PermutationPermutation
Instruction Behavior
VCOMPRESS.VM uses the explicit vs1 mask to select elements from vs2 and writes the selected elements contiguously from vd[0] in original order; it is encoded as an unmasked instruction, and destination elements after the packed result are tail elements.
VCOMPRESS.VM Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VCOMPRESS uses the explicit vs1 selection mask to pack selected vs2 elements in order starting at vd[0].
Instruction input
vcompress.vm
vm
1
fixed unmasked encoding, not a syntax operandRequire valid vtype, enabled VS, and supported SEW; VL=0 updates nothing, including tails. Steps are teaching stages, not processor cycles.
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. Full V requires VLEN≥128; with LMUL=m1 this model uses VLEN=VLMAX×SEW=256. A nonzero vstart for VCOMPRESS.VM raises an illegal instruction exception, so it is not offered as an executable input.
OP-V encodingvcompress.vm
funct6
010111
vm
1
vs2
01000
vs1
00000
funct3
010
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0002
0x0007
0x000c
0x0011
0x0016
0x001b
0x0020
0x0025
pack
pack
pack
pack
pack
pack
pack
pack
vs1
1
0
1
1
1
0
1
1
v4
...
...
...
...
...
...
tail
tail
Current step
Show OP-V 32-bit encoding fields
vcompress.vm uses OP-V encoding. The animation places fixed fields, register fields, vm, and the vs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, element-index/packing/select/move rearrangement integer mask compress, boundary/selection rules, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
vcompress.vm performs stable compaction of source lanes with vs1=1 within vl: the first selected element writes vd[0], the second writes vd[1], and so on.
OP-V encoding uses funct6=010111, funct3=010, and vm=1.
vs1 is the selection-mask operand; this instruction has no separate execution mask.
Destination elements after the packed writes are tail elements governed by vtype.vta.
Encodings where vd overlaps vs2 or vs1 are reserved; a source register cannot be read as both SEW data and an EEW=1 selection mask.
The official specification requires vcompress.vm to raise an illegal-instruction exception when vstart is nonzero.
Vector Execution Context
vs2 supplies SEW-wide source elements; vs1 is the explicit EEW=1 selection mask. Select from the first vl elements and pack in source order starting at vd[0].
vm is fixed to 1; vm=0 is reserved, and the syntax has no additional v0.t execution mask.
vd cannot overlap vs2 or vs1; vs2 and vs1 cannot read one register at different EEWs. Destination elements after the packed result are tails governed by vta.
Require V, supported vtype, and vstart=0; nonzero vstart raises illegal-instruction, with traps reporting vstart=0.
Common Usage Scenarios
Sparse Compression
Assume V with supported e32,m1 and VLMAX≥4, a0=4, and v8=[5,20,-3,40]. The example compare generates selection bits 0101 in lane order 0..3; v12 begins [20,40] after compaction, with subsequent ta tails not assumed zero.
Stream Compaction
Assume V with supported e32,m1 and VLMAX≥4, a0=4, and v8=[5,20,-3,40]. The example compare generates selection bits 0101 in lane order 0..3; v12 begins [20,40] after compaction, with subsequent ta tails not assumed zero.
Pre-Use Checklist
Syntax Check
- vs2 supplies SEW-wide source elements; vs1 is the explicit EEW=1 selection mask. Select from the first vl elements and pack in source order starting at vd[0].
- vm is fixed to 1; vm=0 is reserved, and the syntax has no additional v0.t execution mask.
Semantic Check
- vd cannot overlap vs2 or vs1; vs2 and vs1 cannot read one register at different EEWs. Destination elements after the packed result are tails governed by vta.
- Require V, supported vtype, and vstart=0; nonzero vstart raises illegal-instruction, with traps reporting vstart=0.
Pitfalls / Common Confusions
vs1 is the explicit selection mask, not an extra v0.t execution mask.
The number of writes equals the count of set vs1 bits within vl.
Destination elements after the packed result are tail elements; do not assume old values are preserved.
The vd destination register group must not overlap the vs2 source vector register group or the vs1 source mask register.
If vstart is nonzero, vcompress.vm raises an illegal-instruction exception and reports vstart=0.