Does VCOMPRESS.VM use v0 as an execution mask?
No. It is an unmasked instruction; the explicit vs1 operand is the selection mask.
VCOMPRESS.VM
RISC-V VCOMPRESS.VM Instruction Details
Instruction ManualR-typeCompress vs2 elements selected by mask vs1 into contiguous elements at vd start.
Instruction Syntax
vcompress.vm vd, vs2, vs1
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector PermutationPermutation
Instruction Behavior
VCOMPRESS.VM selects active elements from vs2 according to mask vs1 and packs the selected elements contiguously starting at vd. It is an unmasked instruction and cannot be combined with an execution mask; the spec restricts source/destination register-group overlap to avoid overwriting unread source elements.
Quick Understanding & Search Notes
VCOMPRESS.VM uses vs1 as a selection mask to pack selected vs2 elements, preserving order and writing contiguously from vd[0].
The instruction is encoded as an unmasked operation; vs1 is the explicit selection mask and there is no extra v0 execution mask.
Unselected source elements are not written to the packed result; destination elements after the packed result follow tail policy.
Common Usage Scenarios
Sparse Compression
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmsgt.vi v0, v8, 10 vcompress.vm v12, v8, v0».
Stream Compaction
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vmsgt.vi v0, v8, 10 vcompress.vm v12, v8, v0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
vs1 is the selection mask operand, not the normal v0 execution mask.
Destination elements after the packed selected elements are tail elements governed by vta; do not assume old values are preserved.
Source/destination register-group overlap is restricted by the spec.