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VID.V

RISC-V VID.V Instruction Details

Instruction ManualR-type

Writes each active element index i to destination integer vector vd, using the current SEW for each index value.

Instruction Syntax

vid.v vd, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector PermutationPermutation
Related Search Terms
VID.V instructionRISC-V VID.Vvid.v syntaxvid.v encodingRVV element indexvid.v mask

Instruction Behavior

VID.V is the RISC-V V extension element-index generation instruction. For each active body element i, it writes the unsigned element number i to vd[i]; with vm=0 only elements selected by v0.t are updated, while vm=1 updates all body elements within vl. It reads neither memory nor an ordinary source vector.

VID.V Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VID.V reads no source vector and writes each active lane index into an integer vector.

Instruction input
vid.v
reserved
vs2=00000
no source vector
source
No source vector read
VID.V uses lane indexes only
OP-V encodingfunct6 | vm | vs2=00000 | vs1=10001 | funct3 | vd | opcode
funct6
010100
vm
0
vs2(res)
00000
vs1
10001
funct3
010
vd
01100
opcode
1010111
lane
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
v0.t
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
scan
0
off
2
3
4
5
off
7
8
9
10
off
12
13
14
15
v12
...
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Current step

Show OP-V 32-bit encoding fields

vid.v uses OP-V encoding; the vs1 field is fixed to 10001, and the vs2 field is also fixed to reserved value 00000.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active mask-bit scan within vl, and destination integer-vector writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VID.V is a vector index generator: active lane i writes i, while disabled lanes do not produce a deterministic writeback.

Official syntax is `vid.v vd, vm`; OP-V VMUNARY0 encoding uses `funct6=010100`, `funct3=010`, `vs1=10001`, and requires the reserved `vs2` field to be `00000`.
For each active body element i, the result is the element number i, written to the destination integer vector element at the current SEW.
With vm=0, v0.t is the execution mask; elements with v0.t=0 do not write back and should not be understood as writing zero.
The instruction reads no ordinary source vector or memory and is commonly used to construct element indexes for gather, scatter, compress, or conditional selection.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VID.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Sequence Gen

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vid.v v1, v0.t # active vd[i] = i».

Loop Counter

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vid.v v1, v0.t # active vd[i] = i».

Gather Index

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vid.v v1, v0.t # active vd[i] = i».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

VID.V generates element numbers 0,1,2,..., not byte offsets, memory addresses, or byte positions inside a register group.
The syntax has only vd and optional vm; the encoded vs2 field is reserved, not an editable source-vector operand.
With vm=0, body elements whose v0.t bit is 0 do not write a result; those elements follow the current mask policy, and tail elements follow the tail policy.
If an index value is not representable in the current SEW, the low SEW bits are written; learning examples normally choose an SEW that can hold vl-1.

FAQ

Are VID.V indexes byte offsets?

No. VID.V writes the element number i starting from 0; forming byte addresses later requires element width or explicit scaling.

Does VID.V read vs2?

No. VID.V uses the same OP-V class, but its reserved source field must be 00000 and the assembly syntax has no vs2 source operand.

Do masked-off VID.V elements write zero?

They should not be interpreted as deterministic zero. With vm=0 and v0.t=0, the element does not write back and follows the current mask policy; tail elements follow the tail policy.