VMADC.VI

RISC-V VMADC.VI Instruction Details

Q: Does VMADC.VI write the add/subtract result?

No. VMADC.VI writes only each body element's carry-out destination-mask bit; use the corresponding VADC form when an integer sum is required.

Instruction ManualOPIVI

With vm=1, compute each vs2-plus-immediate carry-out and write the Boolean result to mask destination vd.

Instruction Syntax

vmadc.vi vd, vs2, imm

Operand Breakdown

32-bit OP-V: opcode=1010111, funct6=010001, funct3=011 (OPIVI). vd is a one-bit-per-element mask destination, vs2 a SEW source, and imm is -16..15, sign-extended to SEW.

Fixed vm=1, no v0 carry-in and no v0.t syntax operand; every body element writes the unsigned carry-out of vs2+imm, not the integer sum. vd may be v0 and may overlap vs2 at the same start; mask tails are always agnostic.

Mask bit i is bit i in one vector register, independent of LMUL; carry is 1 exactly when the SEW-width unsigned sum exceeds 2^SEW−1.

Require V 1.0, enabled VS, valid vtype, and supported widths. Prestart stays unchanged; body is vstart≤i<vl. VL=0 or vstart≥vl updates no destination, including tails; normal completion resets vstart=0 and leaves vl unchanged.

The animation fixes LMUL=m1, VLEN=4096, vstart=0 and shows only body mask bits, without claiming zero tails.

VVector IntegerCarry/Borrow

Related Search Terms

VMADC.VI instruction RISC-V VMADC.VI vmadc.vi syntax vmadc.vi RVV vmadc.vi carry out vmadc.vi carry mask

Instruction Behavior

VMADC.VI is a RISC-V V vector-immediate add carry-out instruction. It is encoded with vm=1 and, for each body element, computes the carry-out of vs2[i] plus the 5-bit sign-extended immediate and writes it as a destination mask bit. It writes no integer sum and reads no v0 carry-in.

VMADC.VI Decode And Execute Animation

Starts from OP-V encoding fields, then shows how a non-m VMADC form uses vm=1 for all body elements, reads no carry-in, and writes each carry-out to a destination mask bit.

Instruction input

vmadc.vi

vdDestination mask register v0-v31vs2Use v0-v31immUse -16..15

fixed unmasked encoding, not a syntax operand

Execution Context

VLSEWvs2 elementscomma-separated

immediate value

5 -> 0x0005

5-bit signed imm is sign-extended to SEW

The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. VMADC.VI fixes vm=1 with no v0 carry-in; when v0 is specified as a SEW data source, its data is still read. Each body element produces one destination-mask bit.

OP-V encodingvmadc.vi

funct6

010001

vs2

01000

simm5

00101

funct3

011

00100

opcode

1010111

lane

0xffff

0x010b

0x011c

0xfffc

0x013e

0x014f

0xfffe

0x0171

imm

0x0005

active

v4.mask

...

Current step

Show OP-V 32-bit encoding fields

vmadc.vi uses OP-V encoding. The animation places fixed fields, register fields, vm, and the imm field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer carry-out generation, fixed vm=1 with no carry-in, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VMADC.VI generates a carry mask; in m forms, v0 is the carry/borrow input, not an ordinary execution mask.

Destination vd holds a one-bit mask result, one bit per element.

Forms without the m suffix do not read v0 as carry/borrow input.

The immediate is -16..15, sign-extended to SEW; each body element writes carry-out, not the integer sum.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, V 1.0

Vector Execution Context

32-bit OP-V: opcode=1010111, funct6=010001, funct3=011 (OPIVI). vd is a one-bit-per-element mask destination, vs2 a SEW source, and imm is -16..15, sign-extended to SEW.

Mask bit i is bit i in one vector register, independent of LMUL; carry is 1 exactly when the SEW-width unsigned sum exceeds 2^SEW−1.

The animation fixes LMUL=m1, VLEN=4096, vstart=0 and shows only body mask bits, without claiming zero tails.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Multi-Precision Add

Assume RV32/RV64 V; enabled VS, valid vtype, VLEN≥128, and supported widths; vsetvli gives vl=4, vstart=0, ta/ma, unmasked. x10=4; e8,m1; v2=[255,0,254,1]; imm=1 → v1.mask=[1,0,0,0]. Results use source values before writeback. Tails are not guaranteed zero; normal completion resets vstart=0.

BigInt

Carry Propagation

Pre-Use Checklist

Syntax Check

32-bit OP-V: opcode=1010111, funct6=010001, funct3=011 (OPIVI). vd is a one-bit-per-element mask destination, vs2 a SEW source, and imm is -16..15, sign-extended to SEW.
Fixed vm=1, no v0 carry-in and no v0.t syntax operand; every body element writes the unsigned carry-out of vs2+imm, not the integer sum. vd may be v0 and may overlap vs2 at the same start; mask tails are always agnostic.

Semantic Check

Mask bit i is bit i in one vector register, independent of LMUL; carry is 1 exactly when the SEW-width unsigned sum exceeds 2^SEW−1.
Require V 1.0, enabled VS, valid vtype, and supported widths. Prestart stays unchanged; body is vstart≤i<vl. VL=0 or vstart≥vl updates no destination, including tails; normal completion resets vstart=0 and leaves vl unchanged.
The animation fixes LMUL=m1, VLEN=4096, vstart=0 and shows only body mask bits, without claiming zero tails.

Pitfalls / Common Confusions

Carry stored as single mask bit, not full SEW data register

No carry-in in the non-m form; use vmadc.vim/vvm/vxm for carry-in.

Any v0–v31 may be the destination mask register; mask tails are always agnostic, with no element updates when VL=0.

FAQ

Does VMADC.VI write the add/subtract result?