Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VMADC.VI
RISC-V VMADC.VI Instruction Details
Instruction ManualOPIVIWith vm=1, compute each vs2-plus-immediate carry-out and write the Boolean result to mask destination vd.
Instruction Syntax
vmadc.vi vd, vs2, imm
Operand Breakdown
vd: mask destination register, with one carry-out result bit per body element.
vs2 and vs1: same-lane elements are added at the current SEW.
vm: fixed to vm=1; it reads no v0 carry-in and vm is not a syntax operand.
VVector IntegerCarry/Borrow
Instruction Behavior
VMADC.VI is a RISC-V V vector-immediate add carry-out instruction. It is encoded with vm=1 and, for each body element, computes the carry-out of vs2[i] plus the 5-bit sign-extended immediate and writes it as a destination mask bit. It writes no integer sum and reads no v0 carry-in.
VMADC.VI Decode And Execute Animation
Starts from OP-V encoding fields, then shows how a non-m VMADC form uses vm=1 for all body elements, reads no carry-in, and writes each carry-out to a destination mask bit.
Instruction input
vmadc.vi
vm
1
fixed unmasked encoding, not a syntax operandimmediate value
5 -> 0x0005
5-bit signed imm is sign-extended to SEWThe teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. VMADC.VI fixes vm=1, reads no v0 input, and produces one destination-mask bit for each body element.
OP-V encodingvmadc.vi
funct6
010001
vm
1
vs2
01000
simm5
00101
funct3
011
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0xffff
0x010b
0x011c
0xfffc
0x013e
0x014f
0xfffe
0x0171
+
+
+
+
+
+
+
+
imm
0x0005
0x0005
0x0005
0x0005
0x0005
0x0005
0x0005
0x0005
active
1
1
1
1
1
1
1
1
v4.mask
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
vmadc.vi uses OP-V encoding. The animation places fixed fields, register fields, vm, and the imm field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer carry-out generation, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMADC.VI generates a carry mask; in m forms, v0 is the carry/borrow input, not an ordinary execution mask.
Destination vd holds a one-bit mask result, one bit per element.
Forms without the m suffix do not read v0 as carry/borrow input.
Pair with VSBC for multiword subtraction chains.
Vector Execution Context
When reading VMADC.VI, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vi: one vector source and a small immediate participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Multi-Precision Add
Understand this scenario with real code like «vmadc.vi v1, v2, 1».
BigInt
Understand this scenario with real code like «vmadc.vi v1, v2, 1».
Carry Propagation
Understand this scenario with real code like «vmadc.vi v1, v2, 1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPIVI.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Carry stored as single mask bit, not full SEW data register
No carry-in in the non-m form; use vmadc.vim/vvm/vxm for carry-in.
Destination must be mask register; mask tail always agnostic
FAQ
Does VMADC.VI write the add/subtract result?
No. VMADC.VI writes only each body element's carry-out destination-mask bit; use the corresponding VADC form when an integer sum is required.