Is v0 an execution mask in VMSBC.VXM?
No. The corresponding v0 bit is borrow-in arithmetic input.
VMSBC.VXM
RISC-V VMSBC.VXM Instruction Details
Instruction ManualOPIVXVMSBC computes each body element's borrow-out and writes the Boolean result to the destination mask register.
Instruction Syntax
vmsbc.vxm vd, vs2, rs1, v0
Operand Breakdown
Syntax: vmsbc.vxm vd, vs2, rs1, v0; vd is one mask register, vs2 is a SEW data source, and rs1 selects an integer scalar.
32-bit OP-V: opcode=1010111, funct6=010011, funct3=100 (OPIVX). Fixed vm=0.
Compute unsigned vs2[i]-scalar-v0.mask[i]; write 1 iff the pre-truncation difference is negative. XLEN>SEW uses low SEW scalar bits; XLEN<SEW sign-extends. v0 supplies borrow-in; a zero bit still executes.
The mask destination may be v0. Overlap with a SEW source must start at the source group's lowest register; legal different-EEW overlap forces ma/ta. With m1, equal register names are legal. When v0 supplies mask/borrow bits, it cannot also supply SEW data.
Require RV32/RV64 V 1.0, valid vtype, enabled VS, and supported SEW; body is vstart≤i<vl and prestart is unchanged. Every body element writes borrow-out; mask tails are always agnostic. VL=0 updates no destination, including tails. The animation shows only body elements in a fixed legal configuration; steps are not processor cycles.
VVector IntegerCarry/Borrow
Instruction Behavior
VMSBC.VXM is a RISC-V V-extension vector-scalar subtract borrow-out instruction. Each body element subtracts the SEW-width value of x[rs1] from unsigned vs2[i], then subtracts v0.mask[i]. vd.mask[i] is 1 iff the difference before truncation is negative, otherwise 0. It writes borrow bits, not integer differences. Fixed vm=0 uses v0 as borrow-in, not v0.t predication; all body elements execute.
VMSBC.VXM Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMSBC uses each v0 bit as borrow-in and writes each borrow-out as a destination mask bit.
Instruction input
vmsbc.vxm
v0
v0
arithmetic input, not execution maskRequire valid vtype, enabled VS, and supported SEW; VL=0 updates no destination, including tails. VMSBC writes one mask bit per body element; tails are always agnostic. With m1, vd may equal a data source or v0. With borrow-in, v0 cannot also be a SEW data source.
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvmsbc.vxm
funct6
010011
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0000
0x003b
0x004c
0x0003
0x006e
0x007f
0x0002
0x00a1
-bin
-bin
-bin
-bin
-bin
-bin
-bin
-bin
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
bin
1
0
1
1
1
0
1
1
v4.mask
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
vmsbc.vxm uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer borrow-out generation, v0 carry/borrow input, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMSBC.VXM generates only borrow bits: vd.mask[i] = (unsigned(vs2[i]) - unsigned(scalar) - v0.mask[i] < 0).
OP-V: opcode=1010111, funct6=010011, funct3=100 (OPIVX), vm=0.
Use low SEW bits of x[rs1] when XLEN>SEW; sign-extend when XLEN<SEW. Interpret the resulting bits as unsigned.
vd has one bit per element. Tails are always agnostic; VL=0 updates nothing, including tails.
With LMUL=m1, vd may equal a data source or v0. v0 cannot supply both EEW=1 borrow bits and SEW data.
Vector Execution Context
Syntax: vmsbc.vxm vd, vs2, rs1, v0; vd is one mask register, vs2 is a SEW data source, and rs1 selects an integer scalar.
32-bit OP-V: opcode=1010111, funct6=010011, funct3=100 (OPIVX). Fixed vm=0.
Compute unsigned vs2[i]-scalar-v0.mask[i]; write 1 iff the pre-truncation difference is negative. XLEN>SEW uses low SEW scalar bits; XLEN<SEW sign-extends. v0 supplies borrow-in; a zero bit still executes.
The mask destination may be v0. Overlap with a SEW source must start at the source group's lowest register; legal different-EEW overlap forces ma/ta. With m1, equal register names are legal. When v0 supplies mask/borrow bits, it cannot also supply SEW data.
Require RV32/RV64 V 1.0, valid vtype, enabled VS, and supported SEW; body is vstart≤i<vl and prestart is unchanged. Every body element writes borrow-out; mask tails are always agnostic. VL=0 updates no destination, including tails. The animation shows only body elements in a fixed legal configuration; steps are not processor cycles.
Common Usage Scenarios
Multi-Precision Sub
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, and initialized sources; v0 is borrow-in and all body elements execute. v2=[0,7,0xffffffff,4], x11=7, v0.mask=[0,1,0,1] → v1.mask[0..3]=[1,1,0,1]. Only mask bits are written; tails are always agnostic without assumed zeroing.
BigInt
Assume RV32/RV64 V 1.0, enabled VS, valid e32,m1, VLEN≥128, vl=4, vstart=0, and initialized sources; v0 is borrow-in and all body elements execute. v2=[0,7,0xffffffff,4], x11=7, v0.mask=[0,1,0,1] → v1.mask[0..3]=[1,1,0,1]. Only mask bits are written; tails are always agnostic without assumed zeroing.
Pre-Use Checklist
Syntax Check
- Syntax: vmsbc.vxm vd, vs2, rs1, v0; vd is one mask register, vs2 is a SEW data source, and rs1 selects an integer scalar.
- 32-bit OP-V: opcode=1010111, funct6=010011, funct3=100 (OPIVX). Fixed vm=0.
Semantic Check
- Compute unsigned vs2[i]-scalar-v0.mask[i]; write 1 iff the pre-truncation difference is negative. XLEN>SEW uses low SEW scalar bits; XLEN<SEW sign-extends. v0 supplies borrow-in; a zero bit still executes.
- The mask destination may be v0. Overlap with a SEW source must start at the source group's lowest register; legal different-EEW overlap forces ma/ta. With m1, equal register names are legal. When v0 supplies mask/borrow bits, it cannot also supply SEW data.
- Require RV32/RV64 V 1.0, valid vtype, enabled VS, and supported SEW; body is vstart≤i<vl and prestart is unchanged. Every body element writes borrow-out; mask tails are always agnostic. VL=0 updates no destination, including tails. The animation shows only body elements in a fixed legal configuration; steps are not processor cycles.
Pitfalls / Common Confusions
Borrow tests whether the unsigned difference before truncation is negative, not the sign bit after truncation.
v0 is borrow-in; a zero bit still executes that body element.
The destination has one mask bit per element; tails are not guaranteed preserved, while VL=0 leaves the destination unchanged.
FAQ
What result does VMSBC.VXM write?
It writes one destination mask bit for borrow-out.