Does VMV2R.V copy only current vl elements?
No. A whole-register move copies the complete vector-register group, not elements selected by current vl or SEW.
VMV2R.V
RISC-V VMV2R.V Instruction Details
Instruction ManualOPIVICopy the complete bit contents of 2 consecutive complete vector registers, without element selection by current vl, SEW, or v0.t.
Instruction Syntax
vmv2r.v vd, vs2
Operand Breakdown
vd and vs2 start groups of 2 consecutive vector registers, aligned to 2 without passing v31.
32-bit OP-V: opcode=1010111, funct6=100111, funct3=011, vm=1; simm[4:0]=00001 is fixed; no v0.t operand.
vstart=0 copies all bits; nonzero vstart resumes from that element. evl=NREG*VLEN/SEW; vstart≥evl is reserved. vl does not limit copying; vd=vs2 leaves vector state unchanged.
Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off. Successful completion resets vstart to 0.
VVector Data MovementWhole Register Move
Instruction Behavior
VMV2R.V is a RISC-V V whole-register move instruction. With NREG=2, it copies complete bit contents from the vector-register group starting at vs2 to the group starting at vd; the copy is for compiler vector-register shuffling without needing to know or change current vl.
VMV2R.V Decode And Execute Animation
Decode the OP-V whole-register move fields, then copy 2 complete vector registers; current vl and v0.t do not limit the copy range, while SEW is used only to calculate evl.
Instruction input
vmv2r.v
Execution context
EEW=SEW=32 and EMUL=NREG=2, so evl=2*256/32=16. vl does not limit the copy; vstart >= evl is reserved and is not presented as an executable copy.
OP-V whole-register move encodingvmv2r.v
funct6
100111
vm
1
vs2
10000
simm[4:3]
00
simm[2:0] / NREG
001 -> 2
funct3
011
vd
00010
opcode
1010111
v16->v2
whole register 1v16
0x00001000
0x00001011
0x00001022
0x00001033
0x00001044
0x00001055
0x00001066
0x00001077
v2
...
...
...
...
...
...
...
...
v17->v3
whole register 2v17
0x00001100
0x00001111
0x00001122
0x00001133
0x00001144
0x00001155
0x00001166
0x00001177
v3
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
Whole-register moves use the OPIVI encoding form. The animation places fixed fields, the complete simm[4:0] immediate, the source register group, and the destination register group in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, NREG=2 register-group selection, complete register-content copying, and vd writeback. It does not filter by vl, SEW, or v0.t and does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMV2R.V copies the complete bit contents of a whole register group. It is not the same as a VMV.V.V body-element move; vl, SEW, and v0.t do not limit the copy range.
This page follows the official RISC-V V extension for whole-register moves: NREG=2, with simm[2:0]=001 in the OPIVI encoding using the NREG-1 code; the animation shows the full simm[4:0]=00001.
The syntax has only vd and vs2; the vm bit is fixed to 1, and there is no ordinary v0.t execution-mask operand in assembly syntax.
vd and vs2 are register-group starts; each start must satisfy NREG=2 alignment, and the complete group must remain within v0-v31.
The instruction copies complete vector-register bit contents, not active elements interpreted by current vl, SEW, LMUL, or tail/mask policy.
The official operational model uses the current SEW to compute evl: EEW=SEW, EMUL=NREG, and evl=EMUL*VLEN/SEW; this does not mean the copy is filtered element-by-element by current SEW. The ordinary vstart>=vl no-write rule does not apply, and vstart>=evl is reserved.
Full-copy examples assume vstart=0; nonzero vstart resumes from that element. With vd=vs2, vector register state is unchanged; successful completion resets vstart to 0.
Vector Execution Context
vd and vs2 start groups of 2 consecutive vector registers, aligned to 2 without passing v31.
32-bit OP-V: opcode=1010111, funct6=100111, funct3=011, vm=1; simm[4:0]=00001 is fixed; no v0.t operand.
vstart=0 copies all bits; nonzero vstart resumes from that element. evl=NREG*VLEN/SEW; vstart≥evl is reserved. vl does not limit copying; vd=vs2 leaves vector state unchanged.
Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off. Successful completion resets vstart to 0.
Common Usage Scenarios
Compiler register shuffle
Assume enabled V/VS, valid m1, VLEN≥128, initialized sources and vstart=0; NREG=2: v2=v16, v3=v17. Successful completion resets vstart to 0.
Vector register group rearrangement
Assume enabled V/VS, valid m1, VLEN≥128, initialized sources and vstart=0; NREG=2: v2=v16, v3=v17. Successful completion resets vstart to 0.
Complete vector-register group copy
Assume enabled V/VS, valid m1, VLEN≥128, initialized sources and vstart=0; NREG=2: v2=v16, v3=v17. Successful completion resets vstart to 0.
Pre-Use Checklist
Syntax Check
- vd and vs2 start groups of 2 consecutive vector registers, aligned to 2 without passing v31.
- 32-bit OP-V: opcode=1010111, funct6=100111, funct3=011, vm=1; simm[4:0]=00001 is fixed; no v0.t operand.
Semantic Check
- vstart=0 copies all bits; nonzero vstart resumes from that element. evl=NREG*VLEN/SEW; vstart≥evl is reserved. vl does not limit copying; vd=vs2 leaves vector state unchanged.
- Require V 1.0, valid supported vtype and non-Off mstatus.VS; with H and virtualization V=1, vsstatus.VS must also be non-Off. Successful completion resets vstart to 0.
Pitfalls / Common Confusions
The source and destination start registers must satisfy the NREG=2 register-group alignment constraint, and the group must not pass v31.
It has no ordinary vm syntax operand; do not read it as an element-wise move controlled by v0.t.
The copy range is not the current vl body elements and is not determined by current SEW.
FAQ
Can VMV2R.V use a v0.t mask?
No. The syntax has no ordinary vm operand; it is encoded as an unmasked whole-register move.
What does NREG=2 imply for registers?
vd and vs2 name starts of consecutive register groups; each start must be 2-aligned and the group must not pass v31.