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VMV8R.V

RISC-V VMV8R.V Instruction Details

Instruction ManualV-type

Copy the complete bit contents of 8 consecutive complete vector registers, without element selection by current vl, SEW, or v0.t.

Instruction Syntax

vmv8r.v vd, vs2
Operand Breakdown
vd: destination vector-register group start; it must be aligned to NREG and the complete group must not pass v31.
vs2: source vector-register group start; it must be aligned to NREG and the complete group must not pass v31.
There is no ordinary vm/v0.t operand; the instruction copies complete register bit contents, not elements filtered by current vl or SEW.
VVector Data MovementWhole Register Move
Related Search Terms
VMV8R.V instructionRISC-V VMV8R.Vvmv8r.v syntaxvmv8r.v encodingRVV whole-register moveNREG 8 copyvector register group copy

Instruction Behavior

VMV8R.V is a RISC-V V whole-register move instruction. With NREG=8, it copies complete bit contents from the vector-register group starting at vs2 to the group starting at vd; the copy is for compiler vector-register shuffling without needing to know or change current vl.

VMV8R.V Decode And Execute Animation

Decode the OP-V whole-register move fields, then copy 8 complete vector registers; current vl, SEW, and v0.t do not limit the copy range.

Instruction input
vmv8r.v
OP-V whole-register move encodingvmv8r.v
funct6
100111
vm
1
vs2
10000
simm[4:3]
00
simm[2:0] / NREG
111 -> 8
funct3
011
vd
01000
opcode
1010111
v16->v8
whole register 1
v16
0x00001000
0x00001011
0x00001022
0x00001033
0x00001044
0x00001055
0x00001066
0x00001077
v8
...
...
...
...
...
...
...
...
v17->v9
whole register 2
v17
0x00001100
0x00001111
0x00001122
0x00001133
0x00001144
0x00001155
0x00001166
0x00001177
v9
...
...
...
...
...
...
...
...
v18->v10
whole register 3
v18
0x00001200
0x00001211
0x00001222
0x00001233
0x00001244
0x00001255
0x00001266
0x00001277
v10
...
...
...
...
...
...
...
...
v19->v11
whole register 4
v19
0x00001300
0x00001311
0x00001322
0x00001333
0x00001344
0x00001355
0x00001366
0x00001377
v11
...
...
...
...
...
...
...
...
v20->v12
whole register 5
v20
0x00001400
0x00001411
0x00001422
0x00001433
0x00001444
0x00001455
0x00001466
0x00001477
v12
...
...
...
...
...
...
...
...
v21->v13
whole register 6
v21
0x00001500
0x00001511
0x00001522
0x00001533
0x00001544
0x00001555
0x00001566
0x00001577
v13
...
...
...
...
...
...
...
...
v22->v14
whole register 7
v22
0x00001600
0x00001611
0x00001622
0x00001633
0x00001644
0x00001655
0x00001666
0x00001677
v14
...
...
...
...
...
...
...
...
v23->v15
whole register 8
v23
0x00001700
0x00001711
0x00001722
0x00001733
0x00001744
0x00001755
0x00001766
0x00001777
v15
...
...
...
...
...
...
...
...
Current step

Show OP-V 32-bit encoding fields

Whole-register moves use the OPIVI encoding form. The animation places fixed fields, the complete simm[4:0] immediate, the source register group, and the destination register group in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, NREG=8 register-group selection, complete register-content copying, and vd writeback. It does not filter by vl, SEW, or v0.t and does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

VMV8R.V copies the complete bit contents of a whole register group. It is not the same as a VMV.V.V body-element move; vl, SEW, and v0.t do not limit the copy range.

This page follows the official RISC-V V extension for whole-register moves: NREG=8, with simm[2:0]=111 in the OPIVI encoding using the NREG-1 code; the animation shows the full simm[4:0]=00111.
The syntax has only vd and vs2; the vm bit is fixed to 1, and there is no ordinary v0.t execution-mask operand in assembly syntax.
vd and vs2 are register-group starts; each start must satisfy NREG=8 alignment, and the complete group must remain within v0-v31.
The instruction copies complete vector-register bit contents, not active elements interpreted by current vl, SEW, LMUL, or tail/mask policy.
The official operational model uses the current SEW to compute evl: EEW=SEW, EMUL=NREG, and evl=EMUL*VLEN/SEW; this does not mean the copy is filtered element-by-element by current SEW. The ordinary vstart>=vl no-write rule does not apply, and vstart>=evl is reserved.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations, Whole Vector Register Move Instructions

Vector Execution Context

When reading VMV8R.V, focus on whole-register group copying, not ordinary vector-lane execution. It uses whole-register move rules: vd and vs2 name register-group starts, and the complete VLEN-bit contents are copied.

Whole register group

NREG selects the number of consecutive vector registers; vd and vs2 are register-group starts and must be aligned to NREG.

Complete bit copy

All VLEN bits of each source register are copied, not active elements selected by current vl, SEW, LMUL, tail policy, or mask policy.

No v0.t mask

The vm bit is fixed to 1 and the assembly syntax has no ordinary execution-mask operand; v0.t does not disable part of the copy.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Compiler register shuffle

Understand this scenario with real code like «vmv8r.v v8, v16».

Vector register group rearrangement

Understand this scenario with real code like «vmv8r.v v8, v16».

Complete vector-register group copy

Understand this scenario with real code like «vmv8r.v v8, v16».

Pre-Use Checklist

Syntax Check
  • Confirm vd and vs2 are vector-register group starts, not general-purpose registers.
  • Confirm vd/vs2 starts are aligned to NREG and the complete register groups do not pass v31.
Semantic Check
  • Confirm the instruction copies complete vector-register bit contents, not elements filtered by current vl, SEW, or v0.t.
  • Confirm the OPIVI encoding has vm=1 and simm[2:0] selects 1/2/4/8 registers as NREG-1.

Pitfalls / Common Confusions

The source and destination start registers must satisfy the NREG=8 register-group alignment constraint, and the group must not pass v31.
It has no ordinary vm syntax operand; do not read it as an element-wise move controlled by v0.t.
The copy range is not the current vl body elements and is not determined by current SEW.

FAQ

Does VMV8R.V copy only current vl elements?

No. A whole-register move copies the complete vector-register group, not elements selected by current vl or SEW.

Can VMV8R.V use a v0.t mask?

No. The syntax has no ordinary vm operand; it is encoded as an unmasked whole-register move.

What does NREG=8 imply for registers?

vd and vs2 name starts of consecutive register groups; each start must be 8-aligned and the group must not pass v31.