Whole register group
NREG selects the number of consecutive vector registers; vd and vs2 are register-group starts and must be aligned to NREG.
VMV4R.V
RISC-V VMV4R.V Instruction Details
Instruction ManualV-typeCopy the complete bit contents of 4 consecutive complete vector registers, without element selection by current vl, SEW, or v0.t.
Instruction Syntax
vmv4r.v vd, vs2
Operand Breakdown
vd: destination vector-register group start; it must be aligned to NREG and the complete group must not pass v31.
vs2: source vector-register group start; it must be aligned to NREG and the complete group must not pass v31.
There is no ordinary vm/v0.t operand; the instruction copies complete register bit contents, not elements filtered by current vl or SEW.
VVector Data MovementWhole Register Move
Instruction Behavior
VMV4R.V is a RISC-V V whole-register move instruction. With NREG=4, it copies complete bit contents from the vector-register group starting at vs2 to the group starting at vd; the copy is for compiler vector-register shuffling without needing to know or change current vl.
VMV4R.V Decode And Execute Animation
Decode the OP-V whole-register move fields, then copy 4 complete vector registers; current vl, SEW, and v0.t do not limit the copy range.
Instruction input
vmv4r.v
OP-V whole-register move encodingvmv4r.v
funct6
100111
vm
1
vs2
10000
simm[4:3]
00
simm[2:0] / NREG
011 -> 4
funct3
011
vd
00100
opcode
1010111
v16->v4
whole register 1v16
0x00001000
0x00001011
0x00001022
0x00001033
0x00001044
0x00001055
0x00001066
0x00001077
v4
...
...
...
...
...
...
...
...
v17->v5
whole register 2v17
0x00001100
0x00001111
0x00001122
0x00001133
0x00001144
0x00001155
0x00001166
0x00001177
v5
...
...
...
...
...
...
...
...
v18->v6
whole register 3v18
0x00001200
0x00001211
0x00001222
0x00001233
0x00001244
0x00001255
0x00001266
0x00001277
v6
...
...
...
...
...
...
...
...
v19->v7
whole register 4v19
0x00001300
0x00001311
0x00001322
0x00001333
0x00001344
0x00001355
0x00001366
0x00001377
v7
...
...
...
...
...
...
...
...
Current step
Show OP-V 32-bit encoding fields
Whole-register moves use the OPIVI encoding form. The animation places fixed fields, the complete simm[4:0] immediate, the source register group, and the destination register group in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, NREG=4 register-group selection, complete register-content copying, and vd writeback. It does not filter by vl, SEW, or v0.t and does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMV4R.V copies the complete bit contents of a whole register group. It is not the same as a VMV.V.V body-element move; vl, SEW, and v0.t do not limit the copy range.
This page follows the official RISC-V V extension for whole-register moves: NREG=4, with simm[2:0]=011 in the OPIVI encoding using the NREG-1 code; the animation shows the full simm[4:0]=00011.
The syntax has only vd and vs2; the vm bit is fixed to 1, and there is no ordinary v0.t execution-mask operand in assembly syntax.
vd and vs2 are register-group starts; each start must satisfy NREG=4 alignment, and the complete group must remain within v0-v31.
The instruction copies complete vector-register bit contents, not active elements interpreted by current vl, SEW, LMUL, or tail/mask policy.
The official operational model uses the current SEW to compute evl: EEW=SEW, EMUL=NREG, and evl=EMUL*VLEN/SEW; this does not mean the copy is filtered element-by-element by current SEW. The ordinary vstart>=vl no-write rule does not apply, and vstart>=evl is reserved.
Vector Execution Context
When reading VMV4R.V, focus on whole-register group copying, not ordinary vector-lane execution. It uses whole-register move rules: vd and vs2 name register-group starts, and the complete VLEN-bit contents are copied.
Complete bit copy
All VLEN bits of each source register are copied, not active elements selected by current vl, SEW, LMUL, tail policy, or mask policy.
No v0.t mask
The vm bit is fixed to 1 and the assembly syntax has no ordinary execution-mask operand; v0.t does not disable part of the copy.
Common Usage Scenarios
Compiler register shuffle
Understand this scenario with real code like «vmv4r.v v4, v16».
Vector register group rearrangement
Understand this scenario with real code like «vmv4r.v v4, v16».
Complete vector-register group copy
Understand this scenario with real code like «vmv4r.v v4, v16».
Pre-Use Checklist
Syntax Check
- Confirm vd and vs2 are vector-register group starts, not general-purpose registers.
- Confirm vd/vs2 starts are aligned to NREG and the complete register groups do not pass v31.
Semantic Check
- Confirm the instruction copies complete vector-register bit contents, not elements filtered by current vl, SEW, or v0.t.
- Confirm the OPIVI encoding has vm=1 and simm[2:0] selects 1/2/4/8 registers as NREG-1.
Pitfalls / Common Confusions
The source and destination start registers must satisfy the NREG=4 register-group alignment constraint, and the group must not pass v31.
It has no ordinary vm syntax operand; do not read it as an element-wise move controlled by v0.t.
The copy range is not the current vl body elements and is not determined by current SEW.
FAQ
Does VMV4R.V copy only current vl elements?
No. A whole-register move copies the complete vector-register group, not elements selected by current vl or SEW.
Can VMV4R.V use a v0.t mask?
No. The syntax has no ordinary vm operand; it is encoded as an unmasked whole-register move.
What does NREG=4 imply for registers?
vd and vs2 name starts of consecutive register groups; each start must be 4-aligned and the group must not pass v31.