Is VSM3C.VI an element-wise masked operation?
No. It is an element-group crypto instruction and the official syntax has no vm.
VSM3C.VI
RISC-V VSM3C.VI Instruction Details
Instruction ManualV-type (OP-VE / OPMVV)Vector SM3 compression: uimm=0–31 selects the pair of rounds 2×uimm and 2×uimm+1.
Instruction Syntax
vsm3c.vi vd, vs2, uimm
Syntax: vsm3c.vi vd, vs2, uimm; v0–v31 are vector registers; uimm is a five-bit unsigned immediate, 0–31. Fixed vm=1; no v0.t masking.
32-bit OP-VE: funct6=101011[31:26], vm=1[25], vs2[24:20], uimm[19:15], OPMVV=010[14:12], vd[11:7], opcode=1110111[6:0].
Zvksh depends on Zve32x with SEW=32 only. vd supplies eight state words and vs2 supplies w0/w1/w4/w5. Byte-swap every input/output word; uimm selects rounds 2×uimm and 2×uimm+1, replacing vd. Braces run from highest to lowest element index.
EGS=8, EGW=256. vl/vstart not divisible by EGS or unsupported SEW are reserved; LMUL*VLEN<EGW raises illegal-instruction even at vl=0. vd must not overlap vs2. Groups follow LMUL alignment; .vs scalar groups use EMUL=ceil(EGW/VLEN).
Enable vector state with legal supported vtype. Process only active groups with vstart/EGS≤i<vl/EGS; prestart is undisturbed and tails follow vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support. Execution latency must be data-independent.
ZvkshVector CryptoSM3
Instruction Behavior
Byte-swap inputs, perform rounds 2×uimm and 2×uimm+1, then byte-swap eight output words into vd. SEW=32, EGW=256, EGS=8.
VSM3C.VI Decode & Execute Animation
This bounded model shows official ISA-visible data flow for one element group; it does not model a cryptographic protocol or microarchitecture.
vsm3c.vi
Fixed vm=1, OP-VE, OPMVV; EGS=8, EGW=256.
Lists below run from low to high element index; only the active group is shown and tu preserves tails. vd[A..H]=[0,1,2,3,4,5,6,7]; vs2[w0..w7]=[0,1,2,3,4,5,6,7]. Only w0/w1/w4/w5 are used; input/output words are byte-swapped.
funct6=101011vm=1vs2=01000uimm=00000OPMVV=010vd=00100OP-VE=1110111
Execution data path
OP-VE -> funct6 101011 -> vsm3c.vi
result pending
Quick Understanding & Search Notes
VSM3C.VI is an SM3 vector crypto instruction executed over element groups, not an ordinary independent per-element integer operation.
SM3 uses 256-bit element groups; SM4 uses 128-bit element groups.
The official syntax has no vm operand, so v0.t masking is not added.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 33: Vector Cryptography Extensions, Version 1.0The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31: V Standard Extension for Vector Operations, Version 1.0
Vector Execution Context
Syntax: vsm3c.vi vd, vs2, uimm; v0–v31 are vector registers; uimm is a five-bit unsigned immediate, 0–31. Fixed vm=1; no v0.t masking.
32-bit OP-VE: funct6=101011[31:26], vm=1[25], vs2[24:20], uimm[19:15], OPMVV=010[14:12], vd[11:7], opcode=1110111[6:0].
Zvksh depends on Zve32x with SEW=32 only. vd supplies eight state words and vs2 supplies w0/w1/w4/w5. Byte-swap every input/output word; uimm selects rounds 2×uimm and 2×uimm+1, replacing vd. Braces run from highest to lowest element index.
EGS=8, EGW=256. vl/vstart not divisible by EGS or unsupported SEW are reserved; LMUL*VLEN<EGW raises illegal-instruction even at vl=0. vd must not overlap vs2. Groups follow LMUL alignment; .vs scalar groups use EMUL=ceil(EGW/VLEN).
Enable vector state with legal supported vtype. Process only active groups with vstart/EGS≤i<vl/EGS; prestart is undisturbed and tails follow vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support. Execution latency must be data-independent.
Common Usage Scenarios
Crypto & Security
Enable the listed extension and vector state, with legal vtype, SEW=32, VLEN=256, LMUL=1, vl=8, vstart=0 and tu. Initialize the input groups named in the syntax. The example uses uimm=0. Follow the element-group data flow; the animation lists initial values and results. Success resets vstart=0.
Vector Acceleration
Enable the listed extension and vector state, with legal vtype, SEW=32, VLEN=256, LMUL=1, vl=8, vstart=0 and tu. Initialize the input groups named in the syntax. The example uses uimm=0. Follow the element-group data flow; the animation lists initial values and results. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- Syntax: vsm3c.vi vd, vs2, uimm; v0–v31 are vector registers; uimm is a five-bit unsigned immediate, 0–31. Fixed vm=1; no v0.t masking.
- 32-bit OP-VE: funct6=101011[31:26], vm=1[25], vs2[24:20], uimm[19:15], OPMVV=010[14:12], vd[11:7], opcode=1110111[6:0].
Semantic Check
- Zvksh depends on Zve32x with SEW=32 only. vd supplies eight state words and vs2 supplies w0/w1/w4/w5. Byte-swap every input/output word; uimm selects rounds 2×uimm and 2×uimm+1, replacing vd. Braces run from highest to lowest element index.
- EGS=8, EGW=256. vl/vstart not divisible by EGS or unsupported SEW are reserved; LMUL*VLEN<EGW raises illegal-instruction even at vl=0. vd must not overlap vs2. Groups follow LMUL alignment; .vs scalar groups use EMUL=ceil(EGW/VLEN).
- Enable vector state with legal supported vtype. Process only active groups with vstart/EGS≤i<vl/EGS; prestart is undisturbed and tails follow vta. vstart≥vl (including vl=0) changes no destination elements. Success resets vstart; nonzero vstart assumes implementation support. Execution latency must be data-independent.
Pitfalls / Common Confusions
There is no vm operand; this element-group crypto instruction is unmasked.
SEW must be 32, and vl/vstart must be multiples of EGS=8.
VSM3C reserves vd/vs2 register-group overlap.
FAQ
What vtype restriction matters for VSM3C.VI?
SEW must be 32 and LMUL*VLEN must cover a 256-bit element group.