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VSM3C.VI

RISC-V VSM3C.VI Instruction Details

Instruction ManualI-type

Vector SM3 compression round selected by uimm; executes as an unmasked element-group crypto instruction.

Instruction Syntax

vsm3c.vi vd, vs2, uimm

Operand Breakdown

vd: destination vector register group.

vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.

vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.

ZvkshVector CryptoSM3

Related Search Terms

vsm3c.vi instruction RISC-V vsm3c.vi vsm3c.vi syntax vsm3c.vi encoding vsm3c.vi vector SM3 vsm3c.vi SM3 vsm3c.vi element group

Instruction Behavior

VSM3C.VI is a vector SM3 compression round selected by uimm instruction. SM3 forms use SEW=32, EGW=256, and EGS=8.

Quick Understanding & Search Notes

VSM3C.VI is an SM3 vector crypto instruction executed over element groups, not an ordinary independent per-element integer operation.

SM3 uses 256-bit element groups; SM4 uses 128-bit element groups.

The official syntax has no vm operand, so v0.t masking is not added.

RISC-V Unprivileged ISA Manual: Vector Cryptography Extensions 1.0 RISC-V Unprivileged ISA Manual: V standard vector extension

Vector Execution Context

When reading VSM3C.VI, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vi: one vector source and a small immediate participate.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Crypto & Security

Understand this scenario with real code like «vsm3c.vi vd, vs2, uimm».

Vector Acceleration

Understand this scenario with real code like «vsm3c.vi vd, vs2, uimm».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is I-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

There is no vm operand; this element-group crypto instruction is unmasked.

SEW must be 32, and vl/vstart must be multiples of EGS=8.

Watch vd input/output use and the official register-group overlap restrictions.

FAQ

Is VSM3C.VI an element-wise masked operation?

No. It is an element-group crypto instruction and the official syntax has no vm.

What vtype restriction matters for VSM3C.VI?

SEW must be 32 and LMUL*VLEN must cover a 256-bit element group.