Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VSM3ME.VV
RISC-V VSM3ME.VV Instruction Details
Instruction ManualR-typeVector SM3 message expansion; executes as an unmasked element-group crypto instruction.
Instruction Syntax
vsm3me.vv vd, vs2, vs1
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
ZvkshVector CryptoSM3
Instruction Behavior
VSM3ME.VV is a vector SM3 message expansion instruction. SM3 forms use SEW=32, EGW=256, and EGS=8.
Quick Understanding & Search Notes
VSM3ME.VV is an SM3 vector crypto instruction executed over element groups, not an ordinary independent per-element integer operation.
SM3 uses 256-bit element groups; SM4 uses 128-bit element groups.
The official syntax has no vm operand, so v0.t masking is not added.
Vector Execution Context
When reading VSM3ME.VV, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vv: two vector sources participate element by element.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «vsm3me.vv vd, vs2, vs1».
Vector Acceleration
Understand this scenario with real code like «vsm3me.vv vd, vs2, vs1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
There is no vm operand; this element-group crypto instruction is unmasked.
SEW must be 32, and vl/vstart must be multiples of EGS=8.
Watch vd input/output use and the official register-group overlap restrictions.
FAQ
Is VSM3ME.VV an element-wise masked operation?
No. It is an element-group crypto instruction and the official syntax has no vm.
What vtype restriction matters for VSM3ME.VV?
SEW must be 32 and LMUL*VLEN must cover a 256-bit element group.