Is VSM3ME.VV an element-wise masked operation?
No. It is an element-group crypto instruction and the official syntax has no vm.
VSM3ME.VV
RISC-V VSM3ME.VV Instruction Details
Instruction ManualR-typeVector SM3 message expansion; executes as an unmasked element-group crypto instruction.
Instruction Syntax
vsm3me.vv vd, vs2, vs1
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZvkshVector CryptoSM3
Instruction Behavior
VSM3ME.VV is a vector SM3 message expansion instruction. SM3 forms use SEW=32, EGW=256, and EGS=8.
Quick Understanding & Search Notes
VSM3ME.VV is an SM3 vector crypto instruction executed over element groups, not an ordinary independent per-element integer operation.
SM3 uses 256-bit element groups; SM4 uses 128-bit element groups.
The official syntax has no vm operand, so v0.t masking is not added.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «vsm3me.vv vd, vs2, vs1».
Vector Acceleration
Understand this scenario with real code like «vsm3me.vv vd, vs2, vs1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
There is no vm operand; this element-group crypto instruction is unmasked.
SEW must be 32, and vl/vstart must be multiples of EGS=8.
Watch vd input/output use and the official register-group overlap restrictions.
FAQ
What vtype restriction matters for VSM3ME.VV?
SEW must be 32 and LMUL*VLEN must cover a 256-bit element group.