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CSR Bit Fields

RISC-V hedelegh CSR Register

Address 0x612Privilege HypervisorAccess HRW / 32 bits (RV32 only)Hypervisor and virtualization CSRs

hedelegh is the RV32 upper-32-bit alias CSR for hedeleg.

Related Search Terms
hedelegh CSRhedelegh 0x612hedeleg RV32 upper half
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map

Understand hedelegh By Bit Fields

1 key fields
31:0 (CSR bits 63:32 of hedeleg)

HEDELEG_HIGH

Writable or read-only zero

Alias for the upper half of hedeleg. Each hedeleg bit is writable or read-only zero; a corresponding synchronous exception is further delegated to VS when V=1 before the trap, it was delegated to HS by medeleg, and the hedeleg bit is set.

HEDELEG_HIGH (bits 31:0 (CSR bits 63:32 of hedeleg)) — Alias for the upper half of hedeleg. Each hedeleg bit is writable or read-only zero; a corresponding synchronous exception is further delegated to VS when V=1 before the trap, it was delegated to HS by medeleg, and the hedeleg bit is set.

What This Field Controls

  • - Alias for the upper half of hedeleg. Each hedeleg bit is writable or read-only zero; a corresponding synchronous exception is further delegated to VS when V=1 before the trap, it was delegated to HS by medeleg, and the hedeleg bit is set.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

What To Check First When Reading This CSR

  • - It exists only when H is implemented and XLEN=32.
  • - hedeleg further delegates only VS/VU synchronous exceptions that would trap to HS; traps from HS or M are not delegated through hedeleg.

Risk Checks Before Writing

  • - Treat an unsupported or non-delegable bit as read-only zero; do not assume every exception-cause bit is writable.

Put It Back Into A Real Flow

1

Confirm H and RV32.

2

Confirm that hedeleg may delegate the exception.

3

Read or write the alias bit to access hedeleg[63:32].