RISC-V sieh CSR Register

Address 0x114Privilege SupervisorAccess RW / RV32 only / 32Supervisor status, trap, and interrupt CSRs

sieh (0x114) is the AIA RV32 high-half Supervisor interrupt-enable CSR for the upper 32 bits of sie.

Related Search Terms

sieh CSR sieh 0x114 sie high half AIA enable RV32 interrupt

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

SIE_63_3231:0SRW/RO0

Field Map

Understand sieh By Bit Fields

1 key fields

31:0

SIE_63_32

SRW/RO0

AIA RV32 high-half access window for sie[63:32]; a bit must be writable if its interrupt can become pending, otherwise it is read-only zero. If Smstateen is implemented and mstateen0.AIA=0, access below M-mode raises an illegal-instruction exception.

SIE_63_32 (bits 31:0) — AIA RV32 high-half access window for sie[63:32]; a bit must be writable if its interrupt can become pending, otherwise it is read-only zero. If Smstateen is implemented and mstateen0.AIA=0, access below M-mode raises an illegal-instruction exception.

What This Field Controls

- AIA RV32 high-half access window for sie[63:32]; a bit must be writable if its interrupt can become pending, otherwise it is read-only zero. If Smstateen is implemented and mstateen0.AIA=0, access below M-mode raises an illegal-instruction exception.

Common Values

sieh high-half enable bits

0Disabled

Only for official AIA-defined RV32 sie[63:32] high-half interrupt-enable bits implemented as valid: 0 means the corresponding interrupt is disabled; unimplemented bits may read as zero.

1Enabled

Only for official AIA-defined RV32 sie[63:32] high-half interrupt-enable bits implemented as valid: 1 means the corresponding interrupt is enabled; delivery also depends on the pending bit, sstatus.SIE/privilege rules, and interrupt-controller state.

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Official Basis & Search Notes

sieh is the RV32 high-half access point for sie; it extends the Supervisor interrupt-enable bitmap.

AIA widens supervisor-level sie/sip to 64 bits and adds sieh/siph high-half CSRs on RV32.

Interpret sieh through the corresponding sie[63:32] interrupt-enable bits.

If Smstateen is implemented and mstateen0.AIA=0, access to sieh below M-mode raises an illegal-instruction exception; a virtual-machine access blocked by hstateen0.AIA raises a virtual-instruction exception.

Interrupt delivery still depends on pending bits, enable bits, sstatus.SIE/current privilege mode, and interrupt-controller state.

RISC-V Privileged Architecture Manual - CSR table RISC-V Advanced Interrupt Architecture - CSR chapter

What To Check First When Reading This CSR

- First confirm that the hart implements the extension containing sieh; unimplemented or insufficiently privileged CSR accesses raise an illegal-instruction exception.
- Use address 0x114, the lowest access privilege, and the official access class to decide whether software may access it directly.
- Do not assume fixed values for reserved, WPRI, or WARL fields; interpret them according to the specification and implementation.

Risk Checks Before Writing

- When writing sieh, modify only the officially defined target fields and preserve unchanged bits.
- Handle WARL, WPRI, and reserved fields according to the official specification; do not overwrite the whole CSR as an ordinary integer.

Put It Back Into A Real Flow

In an RV32 + AIA environment, use sieh to access the high interrupt-enable bits sie[63:32].

Set only high interrupt-enable bits supported by the implementation; unimplemented bits may be read-only zero.

Combine it with sip/siph pending bits, sstatus.SIE/current privilege mode, and interrupt-controller state to determine delivery.

FAQ

Does sieh trigger interrupts by itself?

No. It only provides high enable state; interrupt delivery also requires the matching pending bit and the standard S-mode interrupt-delivery rules.