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CSR Bit Fields

RISC-V sieh CSR Register

Address 0x114Privilege SupervisorAccess RW / RV32 only / 32Supervisor status, trap, and interrupt CSRs

sieh (0x114) is the AIA RV32 high-half Supervisor interrupt-enable CSR for the upper 32 bits of sie.

Related Search Terms
sieh CSRsieh 0x114sie high halfAIA enableRV32 interrupt
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
SIE_63_3231:0RW / per enable bit
Field Map

Understand sieh By Bit Fields

1 key fields
31:0

SIE_63_32

RW / per enable bit

RV32 access window for sie[63:32]; exact writability depends on the corresponding enable bit and AIA/implementation definition.

SIE_63_32 (bits 31:0) — RV32 access window for sie[63:32]; exact writability depends on the corresponding enable bit and AIA/implementation definition.

What This Field Controls

  • - RV32 access window for sie[63:32]; exact writability depends on the corresponding enable bit and AIA/implementation definition.

Common Values

sieh high-half enable bits
0Disabled

Only for official AIA-defined RV32 sie[63:32] high-half interrupt-enable bits implemented as valid: 0 means the corresponding interrupt is disabled; reserved, undefined, or unimplemented bits do not have this fixed meaning.

1Enabled

Only for official AIA-defined RV32 sie[63:32] high-half interrupt-enable bits implemented as valid: 1 means the corresponding interrupt is enabled; delivery also depends on pending, global interrupt, delegation, and interrupt-controller state.

↗Open Official Manual
Official Basis & Search Notes

sieh is the RV32 high-half access point for sie; it extends the Supervisor interrupt-enable bitmap.

AIA adds supervisor-level CSR state including sieh/siph.
Interpret sieh through the corresponding high interrupt-enable bits.
Interrupt delivery still depends on pending bits, enable bits, global SIE/privilege state, and delegation/controller state.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Advanced Interrupt Architecture - IMSIC CSRsRISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

  • - First confirm that the hart implements the extension containing sieh; unimplemented or insufficiently privileged CSR accesses raise an illegal-instruction exception.
  • - Use address 0x114, the lowest access privilege, and the official access class to decide whether software may access it directly.
  • - Do not assume fixed values for reserved, WPRI, WARL, or WLRL fields; interpret them according to the specification and implementation.

Risk Checks Before Writing

  • - When writing sieh, modify only the officially defined target fields and preserve unchanged bits.
  • - Handle WARL, WLRL, WPRI, and reserved fields according to the official specification; do not overwrite the whole CSR as an ordinary integer.

Put It Back Into A Real Flow

1

In an RV32 + AIA environment, use sieh to access the high interrupt-enable bits sie[63:32].

2

Set only high interrupt-enable bits supported by the implementation; preserve undefined or reserved bits as specified.

3

Combine it with sip/siph pending bits, sstatus.SIE, delegation, and interrupt-controller state to determine delivery.

FAQ

Does sieh trigger interrupts by itself?

No. It only provides high enable state; interrupt delivery also requires the matching pending bit and standard interrupt rules.