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CSR Bit Fields

RISC-V stimecmph CSR Register

Address 0x15DPrivilege SupervisorAccess RW / RV32 only / 32Supervisor AIA, timer, and indirect interrupt CSRs

stimecmph (0x15D) is the RV32 CSR for the upper 32 bits of the 64-bit stimecmp value.

Related Search Terms
stimecmph CSRstimecmph 0x15Dstimecmp high halfRV32 timer compareSstc CSR
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
STIMECMP_63_3231:0RW
Field Map

Understand stimecmph By Bit Fields

1 key fields
31:0

STIMECMP_63_32

RW

RV32 access window for stimecmp[63:32].

STIMECMP_63_32 (bits 31:0) — RV32 access window for stimecmp[63:32].

What This Field Controls

  • - RV32 access window for stimecmp[63:32].

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

stimecmph is used only on RV32 to access stimecmp[63:32]; RV64 accesses the full 64-bit timer-compare state through stimecmp.

Sstc defines stimecmp as a 64-bit register on all RV32 and RV64 systems.
On RV32, stimecmp is the low half and stimecmph is the high half.
When menvcfg.STCE=0 or mcounteren.TM=0, accesses to stimecmp/stimecmph below M-mode raise illegal-instruction exceptions.
Do not treat stimecmph as an independent timer.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - SstcRISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

  • - First confirm that the hart implements Sstc and that menvcfg.STCE and mcounteren.TM permit S-mode access to stimecmp/stimecmph.
  • - Use address 0x15D, the lowest access privilege, and the official access class to decide whether software may access it directly.
  • - Do not assume fixed values for reserved, WPRI, WARL, or WLRL fields; interpret them according to the specification and implementation.

Risk Checks Before Writing

  • - When writing stimecmph, modify only the officially defined target fields and preserve unchanged bits.
  • - Handle WARL, WLRL, WPRI, and reserved fields according to the official specification; do not overwrite the whole CSR as an ordinary integer.

Put It Back Into A Real Flow

1

On RV32, read/write the upper 32 bits of stimecmp.

2

Maintain the full 64-bit compare value together with the low 32 bits in stimecmp.

3

Follow Sstc STIP-update and spurious-interrupt guidance.

FAQ

Is stimecmph used on RV64?

No. It is an RV32-only high-half CSR.