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CSR Bit Fields

RISC-V siph CSR Register

Address 0x154Privilege SupervisorAccess RW / RV32 only / 32Supervisor AIA, timer, and indirect interrupt CSRs

siph (0x154) is the AIA RV32 high-half Supervisor interrupt-pending CSR for the upper 32 bits of sip.

Related Search Terms
siph CSRsiph 0x154sip high halfAIA pendingRV32 interrupt
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
SIP_63_3231:0RW / per pending bit
Field Map

Understand siph By Bit Fields

1 key fields
31:0

SIP_63_32

RW / per pending bit

RV32 access window for sip[63:32]; exact writability depends on the corresponding pending bit and AIA/implementation definition.

SIP_63_32 (bits 31:0) — RV32 access window for sip[63:32]; exact writability depends on the corresponding pending bit and AIA/implementation definition.

What This Field Controls

  • - RV32 access window for sip[63:32]; exact writability depends on the corresponding pending bit and AIA/implementation definition.

Common Values

siph high-half pending bits
0Not pending

Only for official AIA-defined RV32 sip[63:32] high-half interrupt-pending bits implemented as valid: 0 means the corresponding interrupt is not pending; reserved, undefined, or unimplemented bits do not have this fixed meaning.

1Pending

Only for official AIA-defined RV32 sip[63:32] high-half interrupt-pending bits implemented as valid: 1 means the corresponding interrupt is pending; delivery also depends on enable, global interrupt, delegation, and interrupt-controller state.

↗Open Official Manual
Official Basis & Search Notes

siph is the RV32 high-half access point for sip; it is not a separate pending-state bank independent of sip.

AIA adds supervisor-level CSR state including sieh/siph.
Interpret siph as high interrupt-pending bits, not as a new low-numbered interrupt bank.
mstateen0.AIA restricts AIA state access below M-mode; under virtualization, hstateen0.AIA also restricts virtual access to siph/sieh (RV32) and stopi.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Advanced Interrupt Architecture - IMSIC CSRsRISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

  • - First confirm that the hart implements the extension containing siph; unimplemented or insufficiently privileged CSR accesses raise an illegal-instruction exception.
  • - Use address 0x154, the lowest access privilege, and the official access class to decide whether software may access it directly.
  • - Interpret only official AIA-defined and implemented sip[63:32] high-half pending bits as interrupt-pending state; do not assume fixed meaning for reserved, undefined, or unimplemented bits.

Risk Checks Before Writing

  • - When writing siph, modify only official, implemented high-half pending bits that are writable; do not treat read-only-zero, reserved, undefined, or unimplemented bits as writable state.
  • - Before accessing siph, confirm an RV32 + AIA environment and account for mstateen0.AIA and, under virtualization, hstateen0.AIA access restrictions.

Put It Back Into A Real Flow

1

In an RV32 + AIA environment, use siph to read the high pending bits sip[63:32].

2

Interpret pending bits according to the corresponding high interrupt source; do not treat siph as a new low-numbered interrupt space.

3

Handle pending state together with sie/sieh enable bits, sstatus.SIE, possible hideleg constraints, and external interrupt-controller state.

FAQ

How are siph and sip related?

siph is the RV32 access window for the upper 32 bits of sip.