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CSR Bit Fields

RISC-V vsiph CSR Register

Address 0x254Privilege Hypervisor direct / VS aliasAccess HRW / 32-bit RV32 high halfHypervisor and virtualization CSRs

vsiph is the RV32 upper-32-bit CSR for vsip.

Related Search Terms
vsiph CSRvsiph 0x254vsip high halfRV32 VS interrupt
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map

Understand vsiph By Bit Fields

0 key fields
Official Basis & Search Notes

vsiph is the AIA-defined RV32 high-half CSR for vsip[63:32]. RV32 M/HS can use the separate address; an RV32 guest with V=1 uses the siph alias, and access can be restricted by AIA state-enable bits.

vsiph address, access class, and width are checked against the official CSR tables: 0x254, HRW, 32-bit RV32 high half.
vsiph is used only on RV32 to access the upper 32 bits of vsip; AIA lists it as an RV32-only high-half CSR.
mstateen0.AIA controls lower-privilege access to AIA state such as vsiph; hstateen0.AIA controls VM access through siph to vsiph, only when XLEN=32.
When writing, modify only officially writable high-half interrupt bits; read-only-zero, reserved, and unimplemented bits do not gain pending semantics.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Advanced Interrupt Architecture CSR chapter

What To Check First When Reading This CSR

  • - AIA lists vsiph's separate CSR address as HRW, 32 bits wide, and present only as the RV32 high half of vsip.
  • - When V=1, VS-mode reaches vsiph through the siph alias; direct access to the separate VS CSR address raises a virtual-instruction exception.
  • - When Smstateen/Ssstateen are implemented, mstateen0.AIA and hstateen0.AIA can restrict lower-privilege or VM access to this AIA high-half state.

Risk Checks Before Writing

  • - When writing vsiph, modify only officially writable VS-level high-half interrupt bits; read-only-zero, reserved, and unimplemented interrupt bits must follow the official rules.

Put It Back Into A Real Flow

1

RV32 M/HS software may access vsiph through the separate CSR address 0x254.

2

An RV32 guest with V=1 reaches vsiph through the siph alias; when XLEN > 32, siph/sieh high-half accesses do not become ordinary VS high-half CSR accesses under the AIA state-enable rules.

3

Check hideleg/hvien, AIA, and state-enable conditions before interpreting or updating VS-level interrupt bits 32..63.

FAQ

Can VS-mode directly access vsiph's separate CSR address?

No. The H extension substitutes VS state for the corresponding supervisor CSR when V=1; direct access to the separate VS CSR address raises a virtual-instruction exception.

What does vsiph mainly hold?

vsiph holds vsip[63:32]. Those bits have pending meaning only for VS-level interrupts made visible by AIA, hideleg/hvien, or another official definition.