RISC-V vsiph CSR Register

Address 0x254Privilege Hypervisor direct / VS aliasAccess HRW / 32-bit RV32 high halfHypervisor and virtualization CSRs

vsiph is the RV32 upper-32-bit CSR for vsip.

Related Search Terms

vsiph CSR vsiph 0x254 vsip high half RV32 VS interrupt

Bit Overview

Hover for details · Click to jump↗Open Official Manual

bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Reserved63:32VSIPH31:0RW

Field Map

Understand vsiph By Bit Fields

1 key fields

31:0

VSIPH

Upper 32 bits of vsip on RV32. Only officially defined interrupt bits have the 0/1 pending meaning; undefined or reserved bits do not gain that meaning.

VSIPH (bits 31:0) — Upper 32 bits of vsip on RV32. Only officially defined interrupt bits have the 0/1 pending meaning; undefined or reserved bits do not gain that meaning.

What This Field Controls

- Upper 32 bits of vsip on RV32. Only officially defined interrupt bits have the 0/1 pending meaning; undefined or reserved bits do not gain that meaning.

Common Values

0Not pending

Only for officially defined RV32 high-half virtual supervisor interrupt bits: 0 means that bit is not pending; undefined, reserved, or read-only-zero bits follow the official rules.

1Pending

Only for officially defined RV32 high-half virtual supervisor interrupt bits: 1 means that bit is pending; delivery also depends on vsie/vsieh and vsstatus.SIE. Undefined or reserved bits have no fixed 1=pending meaning.

↗Open Official Manual

Official Basis & Search Notes

vsiph is an RV32 VS interrupt high-half CSR. The separate CSR address is for M/HS-side management; when V=1, guest access to the corresponding supervisor CSR is substituted with VS state unless an extension specifies otherwise.

vsiph address, access class, and width are checked against the official CSR tables: 0x254, HRW, 32-bit RV32 high half.

vsiph is used only on RV32 to access the upper 32 bits of vsip.

When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.

RISC-V Privileged Architecture Manual - CSR table RISC-V Advanced Interrupt Architecture CSR chapter

What To Check First When Reading This CSR

- vsiph's separate CSR address is in the official HRW access class; a VS/VU guest normally reaches VS state through the corresponding supervisor CSR alias.
- Before reading it, confirm that the defining extension such as H, AIA, Sstc, Smstateen, or Smcsrind is implemented.

Risk Checks Before Writing

- When writing vsiph, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

M/HS software may access the VS copy through the separate CSR address.

When V=1, guest access to the corresponding supervisor CSR aliases to VS state; direct access to the separate VS CSR address raises a virtual-instruction exception.

Update only official fields and do not treat VS state as ordinary HS supervisor state.

FAQ

Can VS-mode directly access vsiph's separate CSR address?

No. The H extension substitutes VS state for the corresponding supervisor CSR when V=1; direct access to the separate VS CSR address raises a virtual-instruction exception.

What does vsiph mainly hold?

vsiph holds vsip upper 32 bits, allowing the hypervisor to manage guest-supervisor trap, status, or execution context.