RISC-V hidelegh CSR Register

Address 0x613Privilege HypervisorAccess HRW / 32-bit RV32 high halfHypervisor and virtualization CSRs

hidelegh is the RV32 upper-32-bit CSR for hideleg.

Related Search Terms

hidelegh CSR hidelegh 0x613 hideleg high half RV32 delegation

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Reserved63:32HIDELEG_HIGH31:0RW

Field Map

Understand hidelegh By Bit Fields

1 key fields

31:0

HIDELEG_HIGH

Upper 32 bits of hideleg on RV32. The 0/1 delegation meaning applies only to writable, delegable RV32 high-half interrupt cause bits.

HIDELEG_HIGH (bits 31:0) — Upper 32 bits of hideleg on RV32. The 0/1 delegation meaning applies only to writable, delegable RV32 high-half interrupt cause bits.

What This Field Controls

- Upper 32 bits of hideleg on RV32. The 0/1 delegation meaning applies only to writable, delegable RV32 high-half interrupt cause bits.

Common Values

0Not delegated

Only for writable, delegable RV32 high-half interrupt cause bits: 0 means not further delegated to VS-mode; unimplemented, non-delegable, or read-only-zero bits should not be interpreted with fixed delegation semantics.

1Delegated to VS-mode

Only for writable, delegable RV32 high-half interrupt cause bits: 1 means further delegated to VS-mode when Hypervisor delegation conditions are met; unimplemented, non-delegable, or read-only-zero bits should not be interpreted with fixed delegation semantics.

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Official Basis & Search Notes

hidelegh is an RV32 hypervisor delegation high-half CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

hidelegh address, access class, and width are checked against the official CSR tables: 0x613, HRW, 32-bit RV32 high half.

hidelegh is used only on RV32 to access the upper 32 bits of hideleg.

When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.

RISC-V Privileged Architecture Manual - CSR table RISC-V Privileged Architecture Manual - Hypervisor extension

What To Check First When Reading This CSR

- hidelegh is a Hypervisor-level CSR; its separate address is in the official HRW access class.
- Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

- When writing hidelegh, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hidelegh be accessed through a supervisor CSR alias?

Do not treat hidelegh as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.