RISC-V hviph CSR Register

Address 0x655Privilege HypervisorAccess HRW / 32-bit RV32 high halfHypervisor and virtualization CSRs

hviph is a upper 32 bits of hvip.

Related Search Terms

hviph CSR hviph 0x655 RISC-V AIA hvip upper half virtual interrupt

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Reserved63:32HVIP_HIGH31:0RW

Field Map

Understand hviph By Bit Fields

1 key fields

31:0

HVIP_HIGH

hviph fields for hvip upper half; detailed encoding follows the AIA specification.

HVIP_HIGH (bits 31:0) — hviph fields for hvip upper half; detailed encoding follows the AIA specification.

What This Field Controls

- hviph fields for hvip upper half; detailed encoding follows the AIA specification.

Common Values

hviph high-half pending bits

0Not pending

Only for official AIA-defined RV32 hvip[63:32] high-half virtual-interrupt pending bits implemented as valid: 0 means the corresponding interrupt is not pending; reserved, undefined, or unimplemented bits do not have this fixed meaning.

1Pending

Only for official AIA-defined RV32 hvip[63:32] high-half virtual-interrupt pending bits implemented as valid: 1 means the corresponding interrupt is pending; delivery also depends on enable, global interrupt, delegation, virtualization, and interrupt-controller state.

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Official Basis & Search Notes

hviph is an AIA virtual-interrupt CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

hviph address, access class, and width are checked against the official CSR tables: 0x655, HRW, 32-bit RV32 high half.

AIA defines hypervisor virtual-interrupt CSRs that augment hvip for injecting interrupts into VS level.

Exact fields and priority encoding are interpreted by the AIA VS-level interrupt rules.

When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.

RISC-V Privileged Architecture Manual - CSR table RISC-V Advanced Interrupt Architecture CSR chapter RISC-V AIA VS-level interrupts

What To Check First When Reading This CSR

- hviph is a Hypervisor-level CSR; its separate address is in the official HRW access class.
- Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

- When writing hviph, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hviph be accessed through a supervisor CSR alias?

Do not treat hviph as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.

Can state-enable CSRs control access to hviph?

When Smstateen and AIA are implemented, AIA, IMSIC, or CSRIND bits in mstateen0/hstateen0 may control lower-privilege or VM access to related AIA state.